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| techwell, inc. 1 rev a 11/20/2009 TW8823 -- tft flat panel controller with built-in 3d video decoder, triple adcs , dual pip and 16-bit osd support datasheet from techwell, inc. information may change without notice disclaimer this document provides technical information for th e user. techwell inc. reserves the right to modify the information in this document as necessary. the cust omer should make sure that they have the most recen t data sheet version. techwell inc. holds no responsibilit y for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. techwell inc. respects valid patent rights of third parties and d oes not infringe upon or assist others to infringe upon such rights.
TW8823 ? tft flat panel controller techwell, inc. 2 rev a 11/20/2009 introduction....................................... ..............................................10 applications....................................... ................................................... ..10 analog rgb inputs.................................. ...........................................10 dual digital inputs support ........................ ........................................10 built-in microcontroller........................... ..............................................10 tft panel support.................................. ...........................................11 on screen display.................................. ............................................11 image processing................................... ............................................11 pip function....................................... .................................................11 ddr-sdram.......................................... ...........................................11 host interface..................................... .................................................11 clock generation................................... .............................................11 power management................................... ........................................11 miscellaneous ...................................... ...............................................11 order information.................................. .........................................12 functional description ............................. .....................................15 overview ........................................... ................................................... ...15 analog front-end................................... ...............................................15 video source selection............................. .........................................16 clamping and automatic gain control................ .............................16 video decoder ...................................... .................................................17 sync processor..................................... ..............................................17 color decoding..................................... ..............................................17 automatic standard detection....................... .....................................18 video format support............................... ..........................................18 analog rgb / ypbpr processor ....................... .................................19 analog front-end................................... .............................................19 sync processor..................................... ..............................................19 component processor................................ .......................................19 touch screen controller ............................ .........................................19 digital input support.............................. ...............................................19 tft panel support.................................. ..............................................20 dithering.......................................... ................................................... ..20 lvds out put format................................ ...........................................20 lvds color mapping................................. ........................................21 image control...................................... ................................................... 22 input image control................................ ............................................22 image scaling ...................................... ...............................................22 display timing..................................... ................................................25 external ddr sdram interface....................... ..................................25 on screen display.................................. ..............................................26 external osd port.................................. .............................................26 microcontroller interface.......................... ...........................................32 built-in microcontroller........................... ..............................................48 power management................................... ...........................................48 gamma correction................................... ............................................48 memory configuration............................... ...........................................49 memory interface................................... ................................................50 test modes......................................... ................................................... .50 pin diagram........................................ .............................................51 pin description .................................... ...........................................52 parametric information............................. .....................................62 ac/dc electrical parameters........................ ......................................62 filter curves...................................... ..............................................65 anti-alias filter.................................. ................................................... ..65 decimation filter.................................. .................................................65 chroma band pass filter curves..................... ................................66 luma notch filter curve for ntsc and pal........... ........................66 chrominance low-pass filter curve.................. ..............................67 mechanical data 216 lqfp......................... ................................68 TW8823 register summary ............................ ..............................70 general (common for any page)...................... ................................70 global register .................................... ...............................................71 status & interrupt................................. ...............................................73 internal test...................................... ................................................... 73 decoder............................................ ................................................... 74 decoder............................................ ................................................... 75 lcdc ? 3d comb/nr control.......................... ................................75 lcdc ? iirgb (input interface rgb)................. ..............................76 lcdc : adc/llpll................................... ........................................76 lcdc ? main path input cropping .................... .............................. 78 lcdc ? scaling ..................................... ............................................ 78 lcdc ? panel display control....................... .................................. 79 lcdc ? image adjustment............................ ................................... 81 lcdc ? image adjustment............................ ................................... 82 lcdc ? pip1 control................................ ........................................ 83 lcdc ? pip2 control................................ ........................................ 84 lcdc ? pip1/pip2 common control .................... .......................... 85 lcdc ? dv, pip1/pip2 common control................ ....................... 85 lcdc ? pip alpha blending control .................. ............................. 85 lcdc ? osd ......................................... ............................................ 86 osd ................................................ ................................................... . 88 osd interrupt enable, vertical active status ....... ........................... 90 main/sub path osd selection........................ ................................. 90 external osd ....................................... .............................................. 90 lcdc ? gamma & dither & key (waver_top)........... .................... 91 lcdc ? tga & power management...................... ........................ 91 lcdc ? tcon........................................ ........................................... 92 lcdc ? input measurement........................... .................................. 95 lcdc ? input measurement........................... .................................. 95 lcdc ? ddr memory control.......................... ............................... 96 lcdc ? aux control................................. ......................................... 97 ccfl and ledc control.............................. .................................... 98 tsc (touch screen control)......................... ................................... 98 lcdc : lvds....................................... ............................................. 98 lcdc : remocon rx................................. .................................. 99 lcdc ? lopor...................................... ......................................... 99 lcdc ? pll (panel clock)........................... .................................. 100 lcdc ? pll (memory clock).......................... ............................... 100 lcdc ? dac........................................ ........................................... 100 mcu................................................ .................................................. 1 00 global register.................................... ............................................. 103 0x000 ? product id & revision...................... ...................... 103 gpio registers..................................... ........................................... 104 0x040 ~ 0x049 ? gpio registers.................... ............................. 104 0x050 ~ 0x059 ? gpio registers.................... ............................. 104 0x060 ~ 0x069 ? gpio registers.................... ............................. 104 0x070 ~ 0x079 ? gpio registers.................... ............................. 105 0x080 ? test gpo................................... ........................................ 105 0x090 ~ 0x099 ? pull down & up registers........... ...................... 105 0x0a0 ? mode status............................... ...................................... 106 0x0a1 ? dtv input mode ............................. .................................. 107 0x0aa - 0x0ad ? clock control...................... .................... 107 0x0aa ? clock control option....................... ................................. 107 0x0ab ? clock polarity............................ ....................................... 107 status & interrupt................................. ............................................. 109 0x0b0 to 0x0ba ? status and interrupt registers .... .................... 109 0x0b0 ? status register............................ ...................................... 109 0x0b1? status register............................. ...................................... 109 0x0b2? interrupt control register................. ................................ 110 0x0b3 ? interrupt control register................. ................................ 110 0x0b4 ? status register............................ ...................................... 111 0x0b5 ? status register............................ ...................................... 111 0x0b6 ? status register............................ ...................................... 112 0x0b7 ? status register............................ ...................................... 112 0x0b8 ? interrupt mask register.................... ................................ 113 0x0b9 ? interrupt mask register.................... ................................ 113 0x0ba ? irq ........................................ ............................................ 113 internal test...................................... ................................................ 114 0x0c6 ? internal test control...................... ................................... 114 0x0ce ? internal test mode......................... .................................. 115 0x0e0 ? s/w reset.................................. ....................................... 115 decoder ............................................ ................................................ 116 0x0101 ? chip status register (cstatus)............ ..................... 116 0x0102 ? input format (inform)..................... ............................ 116 0x0103 ? reserved .................................. ....................................... 117 0x0104 ? ckhy...................................... ......................................... 117 0x0105 ? reserved .................................. ....................................... 117 0x0106 ? analog control register (acntl)........... ...................... 117 0x0107 ? cropping register, high (crop_hi)......... ................... 117 TW8823 ? tft flat panel controller techwell, inc. 3 rev a 11/20/2009 0x0108 ? vertical delay register, low (vdelay_lo).. ..............118 0x0109 ? vertical active register, low (vactive_lo) ..............118 0x010a ? horizontal delay register, low (hdelay_lo) ...........118 0x010b ? horizontal active register, low (hactive_l o).........118 0x010c ? control register i (cntrl1)............... ...........................118 0x0110 ? brightness control register (bright)...... ............119 0x0111 ? contrast control register (contrast) ...... ........119 0x0112 ? sharpness control register i (sharpness).. .....119 0x0113 ? chroma (u) gain register (sat_u).......... ....................119 0x0114 ? chroma (v) gain register (sat_v).......... ....................119 0x0115 ? hue control register (hue)................ ...........................119 0x0116 ? reserved.................................. ........................................119 0x0117 ? vertical peaking control i................ ................................120 0x0118 ? coring control register (coring) .......... .....................120 0x011c ? standard selection (sdt).................. ............................120 0x011d ? standard recognition (sdtr)............... ........................121 0x011e ? component video format (cvfmt)............ ................121 0x011f ? adc control register ..................... ...............................121 0x0120 ? clamping gain (clmpg)..................... ..........................122 0x0121 ? individual agc gain (iagc)................ ...........................122 0x0122 ? agc gain (agcgain)........................ ...........................122 0x0123 ? white peak threshold (peakwt)............. ...................122 0x0124? clamp level (clmpl)........................ ...............................122 0x0125? sync amplitude (synct)..................... ...........................122 0x0126 ? sync miss count register (misscnt)........ .................122 0x0127 ? clamp position register (pclamp).......... ....................123 0x0128 ? vertical control register................. .................................123 0x0129 ? vertical control ii....................... .......................................123 0x012a ? color killer level control ................ ................................123 0x012b ? comb filter control....................... ..................................123 0x012c ? luma delay and hsync control.............. ...................123 0x012d ? miscellaneous control register i (misc1) .. .................124 0x012e ? miscellaneous control register ii (misc2). ..................124 0x012f ? miscellaneous control iii (misc3) ......... ........................124 0x0130 ? macrovision detection..................... ................................125 0x0131 ? cstatus iii.............................. .....................................125 0x0132 ? hfref ..................................... ........................................125 0x0133 ? miscellaneous control register............ ..........................125 0x0134 ? nsen/ssen/psen/wkth....................... ....................126 0x0135 ? clamp cntl2 ............................... ......................................126 0x0138 ? analog cntl............................... ........................................126 lcdc ? iirgb (input interface rgb)................. ............................127 lcdc : adc/llpll................................... ......................................127 0x02c0 ? llpll input control register.............. ...........................127 0x02c1 ? llpll input detection register............ .........................127 0x02c2 ? llpll control register.................... ..............................128 0x02c3 ? llpll divider high register............... ...........................128 0x02c4 ? llpll divider low register................ ..........................128 0x02c5 ? llpll clock phase register................ .........................128 0x02c6 ? llpll loop control register............... .........................128 0x02c7 ? llpll vco control register................ ........................129 0x02c8 ? llpll vco control register................ ........................129 0x02c9 ? llpll pre coast register.................. ...........................129 0x02ca ? llpll post coast register................. ..........................129 0x02cb ? sog threshold register.................... ...........................129 0x02cc ? scaler sync selection register............ .........................130 0x02ce ? rgb adc misc. register.................... ..........................130 0x02cf ? rgb adc misc2. register................... .........................131 0x02d0 ? clamp gain control register............... ..........................131 0x02d1 ? y channel gain adjust register............ ........................132 0x02d2 ? c channel gain adjust register ............ .......................132 0x02d3 ? v channel gain adjust register............ ........................132 0x02d4 ? clamp mode control register............... ........................132 0x02d5 ? clamp start position register............. ...........................132 0x02d6 ? clamp stop position register.............. ..........................132 0x02d7 ? clamp master location register............ .......................132 0x02d8 ? adc test register......................... ..............................133 0x02d9 ? g clamp reference register................ ........................133 0x02da ? b clamp reference register................ ........................133 0x02db ? r clamp reference register................ ........................133 0x02dc ? hsync width register ...................... .......................... 133 0x02dd ? r channel adc offset register............. ..................... 133 0x02de ? g channel adc offset register............. ..................... 133 0x02df ? b channel adc offset register............. ...................... 133 0x0300 ? dtv1 input control........................ ................................. 134 0x0301 ? dtv1 input control........................ ................................. 134 0x0302 ? dtv1, rgb input control ................... ........................... 135 0x0304 ? dtv1 field detection region............... ......................... 136 0x0306 ? dtv1 vsync delay.......................... ............................... 136 0x0307 ?........................................... ................................................ 136 0x0313 ? test pattern generator control register.. ................... 137 0x0320 ? dtv2 input control........................ ................................. 138 0x0321 ? dtv2 input control........................ ................................. 138 0x0322 ? dtv2, rgb input control ................... ........................... 139 0x0324 ? dtv2 field detection region............... ......................... 140 0x0326 ? dtv2 vsync delay.......................... ............................... 140 0x0327 ?........................................... ................................................ 140 0x0333 ? test pattern generator control register.. ................... 141 lcdc ? main path input cropping .................... ............................ 142 0x0400 ? main scaler control (soft reset, input se lection, etc) register........................................... .................................................. 1 42 0x0410 ~ 0x0411 main scaler active window horizont al start [10:0] registers 0x0410 ? high byte register ....... ....................... 142 0x0411 low byte register........................... ................................... 142 0x0412 ~ 0x0413 main scaler active window horizont al length [10:0] registers 0x0412 ? high byte register ....... ....................... 142 0x0413 ? low byte register......................... .................................. 142 0x0414 ~ 0x0415 main scaler active window vertical start ? odd field [10:0] 0x0414 ? high byte register....... ....................... 143 0x0415 ? low byte register......................... .................................. 143 0x0416 ? main scaler active window vertical start o ffset register ? even field.............................. ......................................... 143 0x0417 ~ 0x0418 main scaler active window vertical length [10:0] registers 0x0417? high byte register ........ ....................... 143 0x0418 ? low byte register......................... .................................. 143 lcdc ? scaling ..................................... .......................................... 144 0x0430 ~ 0x0432 horizontal up scaling factor [16:0 ] registers 0x0430 ? high byte register........................ .................................. 144 0x0431 ? mid byte register......................... ................................... 144 0x0432 ? low byte register......................... .................................. 144 0x0433 ~ 0x0434 horizontal down scaling factor [8: 0] registers 0x0433 ? high byte register........................ .................................. 144 0x0434 ? low byte register......................... .................................. 144 0x0435 ~ 0x0437 vertical scaling factor [17:0] reg isters 0x0435 ? high byte register............................... ......................................... 145 0x0436 ? mid byte register......................... ................................... 145 0x0437 ? low byte register......................... .................................. 145 0x0438 ? horizontal up scaling offset [7:0] regist er.................. 145 0x0439 ? vertical scaling offset [7:0] register (o dd field)........ 145 0x043a ? vertical scaling offset [7:0] register (e ven field)...... 145 0x043b ? misc scaling control register ............ .......................... 145 0x043c ~ 0x043d panorama width registers 0x043c ? high byte register...................................... .............................................. 146 0x043d ? low byte register......................... ................................. 146 0x043e ? horizontal up scaling factor for panorama register 146 0x043f ? horizontal down scaling filter............ ........................... 146 lcdc ? panel display control....................... ................................ 147 0x0470 ? display control register.................. ............................... 147 0x0471 ? panel output signal control register...... ..................... 147 0x0472 ~ 0x0473 panel output hsync period [11:0] re gisters.. 147 0x0472 ? high byte register........................ .................................. 147 0x0473 ? low byte register......................... .................................. 147 0x0474 ? panel output hsync pulse width [7:0] regis ter........... 147 0x0475 ? panel output hsync back porch [7:0] regist er........... 148 0x0476 ~ 0x0477 panel output horizontal active widt h [10:0] registers.......................................... ................................................. 14 8 0x0476 ? high byte register........................ .................................. 148 0x0477 ? low byte register......................... .................................. 148 0x0478 ~ 0x479 panel output vsync period [10:0] reg ister...... 148 0x0478 ? high byte register........................ .................................. 148 TW8823 ? tft flat panel controller techwell, inc. 4 rev a 11/20/2009 0x0479 ? low byte register ......................... ..................................148 0x047a ? panel output vsync pulse width [7:0] regi ster..........148 0x047b ? panel output vsync back porch [7:0] regis ter...........148 0x047c ~ 0x047d panel output vertical active length [10:0] register 0x047c ? high byte register............... ............................149 0x047d ? low byte register......................... ..................................149 0x0480 ~ 0x0481 horizontal non display width [9:0] registers 0x0480 ? high byte register........................ ...................................149 0x0481 ? low byte register ......................... ..................................149 0x0482 ~ 0x0483 horizontal non display width ii [9: 0] independent left/right selection registers 0x0482 ? high byte register........................................... ................................................... 149 0x0483 ? low byte register ......................... ..................................149 0x0484 ? top / bottom display black out register... ...................149 0x0485 ? bottom display black out register......... .......................150 0x0486 ? fpen delay adjustment register............ ......................150 0x0487 ? fphs delay adjustment register............ ......................150 0x0488 ? fpvs delay adjustment register............ ......................150 0x0489 ? panel adjustment selection register ....... .....................150 0x048a ? panel adjustment selection register....... .....................151 0x048b ? internal panel timing adjustment register . .................151 0x048c ? internal panel timing adjustment register. .................151 0x048d ? panel adjustment selection register....... .....................151 0x0490 ~ 0x0491 pixel counter initialization value [12:0] registers (odd field) .............................. .........................................152 0x0490 ? high byte register........................ ...................................152 0x0491 ? low byte register ......................... ..................................152 0x0492 ~ 0x0493 pixel counter initialization value [12:0] registers (even field)............................. .........................................152 0x0492 ? high byte register........................ ...................................152 0x0493 ? low byte register ......................... ..................................152 0x0494 ? line buffer read start location [7:0] regi ster..............152 0x04c0 ~ 0x04c3 internal counter read out registers .............153 0x04c4 ? simulation initialization register........ .............................153 0x04c5 ? simulation initialization data port regist er ...................153 0x04c6 ? data read selection register .............. .........................153 lcdc ? image adjustment ............................ .................................154 0x0500 ? main image adjustment register............ .......................154 0x0501 ? main image adjustment register............ .......................154 0x0502 ? main image adjustment register............ .......................154 0x0503 ? main image adjustment register............ .......................154 0x0504 ? main image adjustment register............ .......................154 0x0505 ? main image adjustment register............ .......................154 0x0506 ? main image adjustment register............ .......................154 0x0507 ? main image adjustment register............ .......................155 0x0508 ? main image adjustment register............ .......................155 0x0509 ? main image adjustment register............ .......................155 0x050a ? main image adjustment register............ ......................155 0x050b ? main image adjustment register............ ......................155 0x050c ? main image adjustment register............ ......................155 0x0510 ? pip1 image adjustment register............ .......................156 0x0511 ? pip1 image adjustment register............ .......................156 0x0512 ? pip1 image adjustment register............ .......................156 0x0513 ? pip1 image adjustment register............ .......................156 0x0514 ? pip1 image adjustment register............ .......................156 0x0515 ? pip1 image adjustment register............ .......................156 0x0516 ? pip1 image adjustment register............ .......................156 0x0517 ? pip1 image adjustment register............ .......................157 0x0518 ? pip1 image adjustment register............ .......................157 0x0519 ? pip1 image adjustment register............ .......................157 0x051a ? pip1 image adjustment register............ ......................157 0x051b ? pip1 image adjustment register............ ......................157 0x051c ? pip1 image adjustment register............ ......................157 0x0520 ? pip2 image adjustment register............ .......................157 0x0521 ? pip2 image adjustment register............ .......................158 0x0522 ? pip2 image adjustment register............ .......................158 0x0523 ? pip2 image adjustment register............ .......................158 0x0524 ? pip2 image adjustment register............ .......................158 0x0525 ? pip2 image adjustment register............ .......................158 0x0526 ? pip2 image adjustment register............ .......................158 0x0527 ? pip2 image adjustment register............ ...................... 158 0x0528 ? pip2 image adjustment register............ ...................... 159 0x0529 ? pip2 image adjustment register............ ...................... 159 0x052a ? image adjustment register................. .......................... 159 0x052b ? pip2 image adjustment register............ ...................... 159 0x052c ? pip2 image adjustment register ............ ..................... 159 0x0530 ? image adjustment register................. ........................... 159 0x0531 ? image adjustment register................. ........................... 160 0x0532 ? image adjustment register................. ........................... 160 0x0533 ? image adjustment register................. ........................... 160 0x0534 ? image adjustment register................. ........................... 160 0x0535 ? image adjustment register................. ........................... 160 0x0536 ? image adjustment register................. ........................... 160 0x0537 ? image adjustment register................. ........................... 160 0x0538 ? image adjustment register................. ........................... 161 0x0539 ? image adjustment register................. ........................... 161 0x053a ? image adjustment register................. .......................... 161 0x0550 ? image adjustment register................. ........................... 161 0x0551 ? image adjustment register................. ........................... 161 0x0552 ? image adjustment register................. ........................... 161 0x0553 ? image adjustment register................. ........................... 161 0x0554 ? image adjustment register................. ........................... 162 0x0555 ? image adjustment register................. ........................... 162 0x0570 ? test pattern generator register........... ......................... 162 lcdc ? pip1 control................................ ...................................... 164 0x0600 ? pip control register...................... ................................. 164 0x0601 ? pip control register...................... ................................. 164 0x0602 ? pip control register...................... ................................. 164 0x0603 ? pip control register...................... ................................. 164 0x0604 ? pip control register...................... ................................. 164 0x0605 ? pip control register...................... ................................. 164 0x0606 ? pip control register...................... ................................. 164 0x0607 ? pip control register...................... ................................. 165 0x0608 ? pip control register...................... ................................. 165 0x0609 ? pip control register...................... ................................. 165 0x060a ? pip control register...................... ................................. 165 0x060b ? pip control register...................... ................................. 165 0x060c ? pip control register ...................... ................................ 165 0x060d ? pip control register ...................... ................................ 165 0x060e ? pip control register...................... ................................. 166 0x060f ? pip control register...................... ................................. 166 0x0610 ? pip control register...................... ................................. 166 0x0611 ? pip control register...................... ................................. 166 0x0612 ? pip control register...................... ................................. 166 0x0613 ? pip control register...................... ................................. 166 0x0614 ? pip control register...................... ................................. 166 0x0615 ? pip control register...................... ................................. 167 0x0616 ? pip control register...................... ................................. 167 0x0617 ? pip control register...................... ................................. 167 0x0618 ? pip control register...................... ................................. 167 0x0619 ? pip control register...................... ................................. 167 0x061a ? pip control register...................... ................................. 167 0x061b ? pip control register...................... ................................. 168 0x061c ? pip control register ...................... ................................ 168 0x061d ? pip control register ...................... ................................ 168 0x061e ? pip control register...................... ................................. 168 0x061f ? pip control register...................... ................................. 168 0x0620 ? pip control register...................... ................................. 168 0x0621 ? pip control register...................... ................................. 168 0x0622 ? pip control register...................... ................................. 169 0x0623 ? pip control register...................... ................................. 169 0x0624 ? pip control register...................... ................................. 169 0x0625 ? pip control register...................... ................................. 169 0x0626 ? pip control register...................... ................................. 169 lcdc ? pip2 control................................ ...................................... 170 0x0630 ? pip2 control register..................... ................................ 170 0x0631 ? pip2 control register..................... ................................ 170 0x0632 ? pip2 control register..................... ................................ 170 0x0633 ? pip2 control register..................... ................................ 170 0x0634 ? pip2 control register..................... ................................ 170 TW8823 ? tft flat panel controller techwell, inc. 5 rev a 11/20/2009 0x0635 ? pip2 control register..................... .................................170 0x0636 ? pip2 control register..................... .................................170 0x0637 ? pip2 control register..................... .................................171 0x0638 ? pip2 control register..................... .................................171 0x0639 ? pip2 control register..................... .................................171 0x063a ? pip2 control register..................... ................................171 0x063b ? pip2 control register..................... ................................171 0x063c ? pip2 control register..................... ................................171 0x063d ? pip2 control register..................... ................................171 0x063e ? pip2 control register..................... ................................172 0x063f ? pip2 control register ..................... ................................172 0x0640 ? pip2 control register..................... .................................172 0x0641 ? pip2 control register..................... .................................172 0x0642 ? pip2 control register..................... .................................172 0x0643 ? pip2 control register..................... .................................172 0x0644 ? pip2 control register..................... .................................172 0x0645 ? pip2 control register..................... .................................173 0x0646 ? pip2 control register..................... .................................173 0x0647 ? pip2 control register..................... .................................173 0x0648 ? pip2 control register..................... .................................173 0x0649 ? pip2 control register..................... .................................173 0x064a ? pip2 control register..................... ................................173 0x064b ? pip2 control register..................... ................................174 0x064c ? pip2 control register..................... ................................174 0x064d ? pip2 control register..................... ................................174 0x064e ? pip2 control register..................... ................................174 0x064f ? pip2 control register ..................... ................................174 0x0650 ? pip2 control register..................... .................................174 0x0651 ? pip2 control register..................... .................................174 0x0652 ? pip2 control register..................... .................................175 0x0653 ? pip2 control register..................... .................................175 0x0654 ? pip2 control register..................... .................................175 0x0655 ? pip2 control register..................... .................................175 0x0656 ? pip2 control register..................... .................................175 lcdc ? pip1/pip2 common control.................... ........................176 0x0660 ? pip1/2 control register................... ................................176 0x0661 ? pip1/2 control register................... ................................176 0x0662 ? pip1/2 control register................... ................................176 0x0663 ? reserved.................................. ........................................176 lcdc ? dv, pip1/pip2 common control................ .....................177 0x0670 ? dual view control register (only for inte rnal and special customer).................................. ............................................177 0x0671 ? pip1/2 control register................... ................................177 0x0672 ? pip1/2, blending control register......... .........................177 0x0673 ? dual view control register (only for inte rnal and special customer).................................. ............................................178 lcdc ? pip alpha blending control.................. ............................179 0x0680 ? pip alpha blending register .............. ...........................179 0x0681 ? pip alpha blending register .............. ...........................179 0x0682 ? pip alpha blending register .............. ...........................179 0x0683 ? pip alpha blending register .............. ...........................179 0x0684 ? pip alpha blending register .............. ...........................179 0x0685 ? pip alpha blending register .............. ...........................179 0x0686 ? pip alpha blending register .............. ...........................179 0x0687 ? pip alpha blending register............... ...........................179 lcdc ? osd......................................... ...........................................180 0x0700 ? 0sg control register...................... ................................180 0x0701 ? osg control register...................... ...............................181 0x0702 ? ........................ data port for mcu write register 182 0x0703 ? osd/osg control register .................. .........................182 0x0704 ~ 0x0705 osd rlc registers................. ........................182 0x0704 ? osd rlc register.......................... ................................182 0x0705 ? osd rlc register......................... ................................182 0x0706 ? osd/osg control register ................. .........................182 0x070b ? bitblt logic register.................... ...................................183 0x070c ~ 0x070d ........................... bitblt mask register 183 0x070c ? high byte register....................... ...................................183 0x070d ? low byte register........................ ..................................183 0x070e ~ 0x070f block fill color................... ................................183 0x070e ? high byte register........................ ...................................183 0x070f ? low byte register......................... .................................. 183 0x0710 ~ 0x071f 8 bit color expansion table ........ .................... 184 0x0710 ? entry 0 register.......................... ..................................... 184 0x0711 ? entry 1 register.......................... ..................................... 184 0x071f ? entry 15 register ......................... ................................... 184 0x0720 ~ 0x073f 16 bit color expansion table....... ................... 184 0x0720 ? entry 0 register.......................... ..................................... 184 0x0721 ? entry 0 register.......................... ..................................... 184 0x0722 ? entry 1 register.......................... ..................................... 184 0x0723 ? entry 1 register......................... ..................................... 184 0x073e ? entry 15 register......................... ................................... 184 0x073f ? entry 15 register ......................... ................................... 184 0x0740 ~ 0x0747 color conversion source color..... ................. 185 0x0740 ? entry 0 register.......................... ..................................... 185 0x0741 ? entry 0 register.......................... ..................................... 185 0x0742 ? entry 1 register.......................... ..................................... 185 0x0743 ? entry 1 register.......................... ..................................... 185 0x0744 ? entry 2 register.......................... ..................................... 185 0x0745 ? entry 2 register.......................... ..................................... 185 0x0746 ? entry 3 register.......................... ..................................... 185 0x0747 ? entry 3 register.......................... ..................................... 185 0x0748 ~ 0x074f color conversion target color...... .................. 186 0x0748 ? entry 0 register.......................... ..................................... 186 0x0749 ? entry 0 register.......................... ..................................... 186 0x074a ? entry 1 register.......................... .................................... 186 0x074b ? entry 1 register.......................... .................................... 186 0x074c ? entry 2 register.......................... .................................... 186 0x074d ? entry 2 register.......................... .................................... 186 0x074e ? entry 3 register.......................... .................................... 186 0x074f ? entry 3 register......................... ..................................... 186 0x0750 ~ 0x0757 selective overwrite................ ........................... 187 0x0750 ? entry 0 register.......................... ..................................... 187 0x0751 ? entry 0 register.......................... ..................................... 187 0x0752 ? entry 1 register.......................... ..................................... 187 0x0753 ? entry 1 register.......................... ..................................... 187 0x0754 ? entry 2 register.......................... ..................................... 187 0x0755 ? entry 2 register.......................... ..................................... 187 0x0756 ? entry 3 register.......................... ..................................... 187 0x0757 ? entry 3 register.......................... ..................................... 187 0x0760 ~ 0x0762 source buffer memory starting addr ess[23:0] registers.......................................... ................................................. 18 8 0x0760 ? high byte register........................ .................................. 188 0x0761 ? mid byte register......................... ................................... 188 0x0762 ? low byte register......................... .................................. 188 0x0763 ? source buffer memory horizontal length [7: 0] register188 0x0764 ~ 0x0765 transfer source horizontal start [1 0:0] registers.......................................... ................................................. 18 8 0x0764 ? high byte register........................ .................................. 188 0x0765 ? low byte register......................... .................................. 188 0x0766 ~ 0x0767 transfer source vertical start [10: 0] registers188 0x0766 ? high byte register........................ .................................. 188 0x0767 ? low byte register......................... .................................. 188 0x0768 ~ 0x0769 transfer horizontal length[11:0] re gisters.... 189 0x0768 ? high byte register........................ .................................. 189 0x0769 ? low byte register......................... .................................. 189 0x076a ~ 0x076b transfer vertical length[11:0] regi sters........ 189 0x076a ? high byte register........................ .................................. 189 0x076b ? low byte register ......................... ................................. 189 0x0770 ~ 0x0772 destination buffer memory starting address[23:0] registers............................ ...................................... 189 0x0770 ? high byte register........................ .................................. 189 0x0771 ? mid byte register......................... ................................... 189 0x0772 ? low byte register......................... .................................. 189 0x0773 ? destination buffer memory horizontal lengt h[7:0] registers 0x0774 ~ 0x0775 transfer destination horizontal sta rt[10:0] registers.......................................... ................................................. 19 0 0x0774 ? high byte register........................ .................................. 190 0x0775 ? low byte register......................... .................................. 190 0x0776 ~ 0x0777 transfer destination vertical start [10:0] registers.......................................... ................................................. 19 0 TW8823 ? tft flat panel controller techwell, inc. 6 rev a 11/20/2009 0x0776 ? high byte register........................ ...................................190 0x0777 ? low byte register ......................... ..................................190 0x0778 ? osd control register ...................... ...............................190 0x0779 ? osd gain control register................. ...........................191 0x077a ? 8 bit osd look up table access control reg ister.....191 0x077b ? 8 bit osd look up table address[7:0] regis ter.........191 0x077c ~ 0x077f 8 bit osd look up table data port[3 1:0] register 192 0x077c ? byte 3 register........................... .....................................192 0x077d ? byte 2 register........................... .....................................192 0x077e ? byte 1 register........................... .....................................192 0x077f ? byte 0 register ........................... .....................................192 0x0780 ? osd window 0 enable register .............. .....................192 0x0781 ~ 0x0782 osd window 0 horizontal start [10:0 ] registers 192 0x0781 ? high byte register........................ ...................................192 0x0782 ? low byte register ......................... ..................................192 0x0783 ~ 0x0784 .... osd window 0 vertical start [10:0] register 193 0x0783 ? high byte register........................ ...................................193 0x0784 ? low byte register ......................... ..................................193 0x0785 ~ 0x0786 osd window 0 horizontal length [11: 0] registers.......................................... ..................................................1 93 0x0785 ? high byte register........................ ...................................193 0x0786 ? low byte register ......................... ..................................193 0x0787 ~ 0x0788 osd window 0 vertical length [11:0 ] registers 193 0x0787 ? high byte register........................ ...................................193 0x0788 ? low byte register ......................... ..................................193 0x0789 ~ 0x078b osd window 0 buffer memory starting address [23:0] register 194 0x0789 ? high byte register........................ ...................................194 0x078a ? mid byte register......................... ...................................194 0x078b ? low byte register......................... ..................................194 0x078c ? osd window 0 buffer memory horizontal leng th [7:0] register 194 0x078d ? osd window 0 buffer memory vertical length [7:0] register 194 0x078e ~ 0x078f osd window 0 image horizontal star t [10:0] registers 194 0x078e ? high byte register........................ ..................................194 0x078f ? low byte register......................... ..................................194 0x0790 ~ 0x0791 osd window 0 image vertical start [ 10:0] register 195 0x0790 ? high byte register........................ ...................................195 0x0791 ? low byte register ......................... ..................................195 0x0792 ....... ? osd window 0 global alpha value [6:0] register 19 5 0x07a0 ? osd window 1 enable register.............. .....................195 0x07a1 ~ 0x07a2 osd window 1 horizontal start [10:0 ] registers 195 0x07a1 ? high byte register........................ ..................................195 0x07a2 ? low byte register......................... ..................................195 0x07a3 ~ 0x07a4 ... osd window 1 vertical start [10:0] registers 196 0x07a3 ? high byte register........................ ..................................196 0x07a4 ? low byte register......................... ..................................196 0x07a5 ~ 0x07a6 osd window 1 horizontal length [11 :0] registers 196 0x07a5 ? high byte register........................ ..................................196 0x07a6 ? low byte register......................... ..................................196 0x07a7 ~ 0x07a8 osd window 1 vertical length [11:0 ] registers 196 0x07a7 ? high byte register........................ ..................................196 0x07a8 ? low byte register......................... ..................................196 0x07a9 ~ 0x07ab osd window 1 buffer memory starting address [23:0] registers 197 0x07a9 ? high byte register........................ ..................................197 0x07aa ? mid byte register......................... ...................................197 0x07ab ? low byte register......................... ..................................197 0x07ac ? osd window 1 buffer memory horizontal leng th [7:0] register 197 0x07ad ? osd window 1 buffer memory vertical length [7:0] register 197 0x07ae ~ 0x07af osd window 1 image horizontal start [10:0] register 197 0x07ae ? high byte register........................ ..................................197 0x07af ? low byte register......................... ..................................197 0x07b~ 0x07b1 osd window 1 image vertical start [10 :0] registers.......................................... ..................................................1 98 0x07b0 ? high byte register........................ ..................................198 0x07b1 ? low byte register......................... ..................................198 0x07b2 ...... ? osd window 1 global alpha value [6:0] register 1 98 0x07c0 ? osd window 4 enable....................... ...........................198 0x07c1 ~ 0x07c2 .......... osd window 4 horizontal start [10:0] 199 0x07c1 ? high byte ................................ ........................................199 0x07c2 ? low byte.................................. ........................................199 0x07c3 ~ 0x07c4 ............ osd window 4 vertical start [10:0] 199 0x07c3 ? high byte................................. ........................................ 199 0x07c4 ? low byte .................................. ....................................... 199 0x07c5 ~ 0x07c6 osd window 4 horizontal length [11 :0]..... 199 0x07c5 ? high byte................................. ........................................ 199 0x07c6 ? low byte .................................. ....................................... 199 0x07c7 ~ 0x07c8 osd window 4 vertical length [11:0 ].......... 200 0x07c7 ? high byte................................. ........................................ 200 0x07c8 ? low byte .................................. ....................................... 200 0x07c9 ~ 0x07cb window 4 buffer memory starting ad dress [23:0] 0x07c9 ? high byte................................. ........................................ 200 0x07ca ? mid byte.................................. ........................................ 200 0x07cb ? low byte.................................. ....................................... 200 0x07cc ? osd window 4 buffer memory horizontal leng th [7:0]200 0x07cd ? osd window 4 buffer memory vertical length [7:0]. 200 0x07ce ~ 0x07cfosd window 4 image horizontal start [10:0]201 0x07ce ? high byte................................. ....................................... 201 0x07cf ? low byte.................................. ....................................... 201 0x07d0 ~ 0x07d1 osd window 4 image vertical start [10:0].. 201 0x07d0 ? high byte................................. ........................................ 201 0x07d1 ? low byte .................................. ....................................... 201 0x07d2 ? osd window 4 global alpha value [6:0 ] .................... 201 0x07d4 ~ 0x07d5 color key 0 for 16 bit osd [15:0].. ................. 202 0x07d4 ? high byte................................. ........................................ 202 0x07d5 ? low byte .................................. ....................................... 202 0x07d6 ~ 0x07d7 color key 1 for 16 bit osd [15:0].. ................. 202 0x07d6 ? high byte................................. ........................................ 202 0x07d7 ? low byte .................................. ....................................... 202 0x07d8 ~ 0x07d9 color key 2 for 16 bit osd [15:0].. ................. 202 0x07d8 ? high byte................................. ........................................ 202 0x07d9 ? low byte .................................. ....................................... 202 0x07da ~ 0x07db color key 3 for 16 bit osd [15:0].. ................ 202 0x07da ? high byte................................. ....................................... 202 0x07db ? low byte.................................. ....................................... 202 0x07dc ? color key 0 alpha value [6:0] ............. ......................... 203 0x07dd ? color key 1 alpha value [6:0] ............. ......................... 203 0x07de ? color key 2 alpha value [6:0]............. .......................... 203 0x07df ? color key 3 alpha value [6:0]............. .......................... 203 osd interrupt enable, vertical active status ....... ......................... 204 0x07f0 ? vertical active status.................... .................................. 204 0x07f1 ? osd busy interrupt enable................. .......................... 204 main/sub path osd selection........................ ............................... 204 0x07f8 ? main/sub path osd selection............... ....................... 204 external osd ....................................... ............................................ 205 0x08f2? external osd control....................... ............................... 205 0x08f3 ? external osd horizontal control.......... ........................ 205 0x08f4 ? external osd clock output delay........... ..................... 205 0x08f5 ? external osd alpha blending level......... .................... 205 0x08f6 ? external osd misc control................ ........................... 206 0x08f7 ? external osd vsync pulse width............ ..................... 206 lcdc ? gamma & dither & key (waver_top)........... .................. 207 0x0900 ? lcdc gamma control register.............. .................... 207 0x0901 ? gamma table address port register........ .................. 207 0x0902 ? gamma table data port register............ ..................... 207 0x0903 ? gamma table data port register............ ..................... 207 0x0910 ? dither option register .................... ................................ 208 0x0920 ? rgb level readout register................ ........................ 209 0x0921 ? rgb level readout register................ ........................ 209 0x0922 ? rgb level readout register................ ........................ 209 0x0923 ? pip alpha blending red key register....... ................... 209 0x0924 ? pip alpha blending green key register..... ................. 209 0x0925 ? pip alpha blending blue key register...... ................... 209 lcdc ? tga & power management...................... ...................... 210 0x0970 ? panel interface control register......... .......................... 210 0x0971 ? panel clock delay register ............... ........................... 210 0x0987 ? pwm control register...................... .............................. 210 0x0988 ? pwm control register...................... .............................. 210 0x0989 ~ 0x098a pwm clock divider registers....... ................. 210 0x0989 ? high byte register........................ .................................. 210 0x098a ? low byte register ........................ ................................. 211 0x098b ? pwm2 control register..................... ............................ 211 TW8823 ? tft flat panel controller techwell, inc. 7 rev a 11/20/2009 0x098c ? pwm2 control register..................... ............................211 0x098d ~ 0x098e pwm2 clock divider registers...... ................211 0x098d ? high byte register....................... ..................................211 0x098e ? low byte register........................ ..................................211 0x09f5 ? panel power pin register................. .............................211 lcdc timing controller configuration registers..... .....................212 0x0a00 ? output mode control register.............. .........................212 0x0a01 ? display control register.................. ...............................212 0x0a02 ? display direction control register........ .........................212 0x0a03 ? control signal polarity selection register .....................213 0x0a04 ? control signal generation method register. ................213 0x0a06 ? panel type select register................ .............................214 0x0a0a ? special lcd module control register....... ...................214 0x0a0b ? revv(tcpolp) / revc(tcpoln) control regist er214 0x0a0c ? vertical active start high register ....... .........................214 0x0a0d ? vertical active start low register........ .........................214 0x0a0e ? vertical active end high register......... .........................214 0x0a0f ? vertical active end low register.......... .........................214 column driver chip control signals relative registe rs...............215 0x0a10 ? polarity control high register............ ............................215 0x0a11 ? polarity control low register............. ............................215 0x0a12 ? load/latch pulse start high register...... .....................215 0x0a13 ? load/latch pulse start low register....... .....................215 0x0a14 ? load/latch pulse width high register...... ...................215 0x0a15 ? load/latch pulse width low register....... ...................215 0x0a1a ? column driver start pulse high register... ..................215 0x0a1b ? column driver start pulse low register.... ..................215 0x0a1c ? column driver start pulse width high regis ter..........215 0x0a1d ? column driver start pulse width low regist er...........215 row driver chip control signals relative registers. ....................216 0x0a20 ? clock start pulse high register........... ..........................216 0x0a21 ? clock start pulse low register ............ .........................216 0x0a22 ? clock start pulse width high register..... .....................216 0x0a23 ? clock start pulse width low register ...... ....................216 0x0a24 ? row start pulse high register ............. .........................216 0x0a25 ? row start pulse low register.............. .........................216 0x0a26 ? row start pulse width high register ....... ....................216 0x0a27 ? row start pulse width low register........ ....................216 0x0a2c ? row output enable high register........... .....................216 0x0a2d ? row output enable low register............ ....................216 0x0a2e ? row output enable width high register..... ................217 0x0a2f ? row output enable width low register...... ................217 0x0a34 ? sharp mode register....................... ...............................217 0x0a35 ? sharp mode register....................... ...............................217 0x0a36 ? sharp mode register....................... ...............................217 0x0a37 ? sharp mode register....................... ...............................217 0x0a38 ? direct mode tclp width, position and step control register........................................... ................................................... 217 0x0a39 ? direct mode tcsp width and step control re gister..217 0x0a3a ? polarity special function register........ .........................217 0x0a3d ? direct mode trsp step control register .... ...............218 0x0a3f ? delta rgb register........................ ................................218 lcdc ? input measurement........................... ................................219 0x0b00 ~ 0x0b01 measurement window horizontal sta rt [10:0] 0x0b00 ? high byte register........................ ..................................219 0x0b01 ? low byte register......................... ..................................219 0x0b02 ~ 0x0b03 measurement window horizontal len gth [11:0] 0x0b02 ? high byte register................. ...............................219 0x0b03 ? low byte register......................... ..................................219 0x0b04 ~ 0x0b05 measurement window vertical start [10:0] 0x0b04 ? high byte register........................ ..................................219 0x0b05 ? low byte register......................... ..................................219 0x0b06 ~ 0x0b07 measurement window vertical lengt h [10:0] 0x0b06 ? high byte register........................ ..................................220 0x0b07 ? low byte register......................... ..................................220 0x0b08 ? measurement input selection, measurement start register........................................... ................................................... 220 0x0b09 ? measurement option, input change detectio n register........................................... ................................................... 220 0x0b0a ? measurement option register.............. .......................220 0x0b10 ~ 0x0b13 phase_r registers 0x0b10 ? byte 3 register221 0x0b11 ? byte 2 register ........................... .................................... 221 0x0b10 ? byte 1 register ........................... .................................... 221 0x0b13 ? byte 0 register ........................... .................................... 221 0x0b14 ~ 0x0b17 phase_g registers 0x0b14 ? byte 3 register221 0x0b15 ? byte 2 register ........................... .................................... 221 0x0b16 ? byte 1 register ........................... .................................... 221 0x0b17 ? byte 0 register ........................... .................................... 221 0x0b18 ~ 0x0b1b phase_b registers 0x0b18 ? byte 3 register222 0x0b19 ? byte 2 register ........................... .................................... 222 0x0b1a ? byte 1 register........................... .................................... 222 0x0b1b ? byte 0 register........................... .................................... 222 0x0b1c ? minimum_r register ........................ ............................ 222 0x0b1d ? minimum_g register....................... ............................ 222 0x0b1e ? minimum_b register........................ ............................. 222 0x0b1f ? maximum_r register........................ ............................ 222 0x0b20 ? maximum_g register........................ ............................ 222 0x0b21 ? maximum_b register........................ ............................ 222 0x0b22 ~ 0x0b23 vertical period registers 0x0b22 ? high byte register........................................... .................................................. 2 23 0x0b23 ? low byte register ......................... ................................. 223 0x0b24 ~ 0x0b25 horizontal period registers 0x0b24 ? high byte register...................................... .............................................. 223 0x0b25 ? low byte register ......................... ................................. 223 0x0b26 ~ 0x0b27 hsync rise to fall registers 0x0b2 6 ? high byte register...................................... .............................................. 223 0x0b27 ? low byte register ......................... ................................. 223 0x0b28 ~ 0x0b29 hsync rise to horizontal active en d 0x0b28 ? high byte register................................. .......................................... 223 0x0b29 ? low byte register ......................... ................................. 223 0x0b2a ~ 0x0b2b vsync high width registers 0x0b2a ? high byte register...................................... .............................................. 224 0x0b2b ? low byte register......................... ................................. 224 0x0b2c ~ 0x0b2d vsync rise position registers 0x0b 2c ? high byte register................................. .......................................... 224 0x0b2d ? low byte register......................... ................................. 224 0x0b2e ~ 0x0b2f horizontal active starting pixel p osition i registers 0x0b2e ? high byte register.............. .......................... 224 0x0b2f ? low byte register......................... ................................. 224 0x0b30 ~ 0x0b31 horizontal active starting pixel p osition ii registers 0x0b30 ? high byte register .............. .......................... 224 0x0b31 ? low byte register ......................... ................................. 224 0x0b32 ~ 0x0b33 horizontal active ending pixel pos ition i registers 0x0b32 ? high byte register .............. .......................... 225 0x0b33 ? low byte register ......................... ................................. 225 0x0b34 ~ 0x0b35 horizontal active ending pixel pos ition ii register 0x0b34 ? high byte register ............... ........................... 225 0x0b35 ? low byte register ......................... ................................. 225 0x0b36 ~ 0x0b37 vertical active starting line i re gisters......... 225 0x0b36 ? high byte register........................ .................................. 225 0x0b37 ? low byte register ......................... ................................. 225 0x0b38 ~ 0x0b39 vertical active starting line ii r egisters 0x0b38 ? high byte register........................ .................................. 225 0x0b39 ? low byte register ......................... ................................. 225 0x0b3a ~ 0x0b3b vertical active ending line i regi sters 0x0b3a ? high byte register........................ ................................. 226 0x0b3b ? low byte register......................... ................................. 226 0x0b3c ~ 0x0b3d vertical active ending line ii reg isters 0x0b3c ? high byte register........................ ................................. 226 0x0b3d ? low byte register......................... ................................. 226 0x0b3e ~ 0x0b3f fifo read starting position regist ers 0x0b3e ? high byte register........................ ................................. 226 0x0b3f low byte register.......................... .................................. 226 0x0b40 ? liminance value ? minimum register........ .................. 226 0x0b41 ? liminance value ? maximum register........ ................ 226 0x0b42 ? liminance value ? average register........ ................... 226 0x0b43 ~ 0x0b45 vertical period in 27 mhz register s 0x0b43 ? high byte register................................. .......................................... 227 0x0b44 ? mid byte register ......................... .................................. 227 0x0b45 ? low byte register ......................... ................................. 227 TW8823 ? tft flat panel controller techwell, inc. 8 rev a 11/20/2009 lcdc ? ddr memory control.......................... .............................228 0x0c00 ? ddr memory control register ............... ......................228 0x0c01 ? ddr memory control register ............... ......................228 0x0c02 ? ddr memory control register ............... ......................228 0x0c03 ? ddr memory control register ............... ......................228 0x0c04 ? ddr memory control register ............... ......................228 0x0c05 ? ddr memory control register ............... ......................228 0x0c06 ? ddr memory control register ............... ......................229 0x0c07 ? ddr memory control register ............... ......................229 0x0c08 ? ddr memory control register ............... ......................229 0x0c09 ? ddr memory control register ............... ......................229 0x0c0a ? ddr memory control register............... ......................229 0x0c0b ? ddr memory control register............... ......................230 0x0c0c ? ddr memory control register............... ......................230 lcdc ? aux control................................. ........................................231 0x0cf0 ? ddr direct r/w control register........... ......................231 0x0cf1 ? ddr direct r/w control register........... ......................231 0x0cf2 ? ddr direct r/w control register........... ......................231 0x0cf3 ? ddr direct r/w control register........... ......................231 0x0cf4 ? ddr direct r/w control register........... ......................231 0x0cf5 ? ddr direct r/w control register........... ......................231 0x0cf6 ? ddr direct r/w control register........... ......................231 0x0cf7 ? ddr direct r/w control register........... ......................232 ccfl and ledc control.............................. ...................................233 0x0d0 ? ccfl/led control i......................... .................................233 0x0d01 ? ccfl/led control i........................ ................................233 0x0d02 ? ccfl threshold and ledc control........... ..................233 0x0d03 ? ccfl/led control ii....................... ................................234 0x0d04 ? ccfl/ledc pwm............................. ............................234 0x0d05 ? ccfl/led dim frequency .................... .......................234 0x0d06 ? ccfl/led dim control ...................... ...........................234 0x0d07 ? ccfl/led pwmtop........................... .........................234 0x0d10 ? control signal generation method register (logic level: 1.8v).............................................. ................................................... ..235 touch screen control............................... .......................................236 0x0d11 ? control signal generation method register (logic level: 1.8v).............................................. ................................................... ..236 0x0d12 ? tsc adc data output....................... ............................236 0x0d13 ? tsc adc data output....................... ............................236 0x0d14 ? tsc start and clock....................... ................................237 0x00 ?adc output read only register (logic level: 1 .8v).........238 note: this read only register is implemented on the top level of this analog ip. the raw data will be read and placed in this register. lvds configuration registers ....................... .................................238 lvds configuration registers ....................... .................................239 0xd40 ? mode 1 setting register.................... ...............................239 0xd41 ? mode 2 setting register.................... ...............................239 0xd42 ? mode 3 setting register.................... ...............................239 remocon_rx......................................... ......................................240 0xda0 ? remocon control0........................... .....................240 0xda1 ? remocon control1........................... .....................240 0xda2 ? remocon enable............................. .........................240 0xda3 ? remocon interrupt.......................... .....................240 0xda4 ? htsystem................................... ...................................241 0xda5 ? htcommand.................................. ...............................241 0xda6 ? updreg3.................................... ....................................241 0xda7 ? updreg2.................................... ....................................241 0xda8 ? updreg1.................................... ....................................241 0xda9 ? updreg0.................................... ....................................241 0xdaa ? rempi...................................... .........................................241 0xdab ? remclkref .................................. ................................241 0xdac ? remclkref.................................. ................................241 0xdad ? updhten.................................... ....................................242 0xdae ? usample.................................... ....................................242 0xdaf ? ulleader ................................... ...................................242 0xdb0 ? ulleader................................... ....................................242 0xdb1 ? uhleader................................... ...................................242 0xdb2 ? uhleader................................... ...................................242 lcdc ? lopor....................................... ........................................243 0xdc0 ? lso power down register.................... .........................243 0xdc1 ? por power down register .................... ....................... 243 lcdc ? pll (panel clock)........................... .................................. 244 0x0dd0 ? pll control register...................... ............................... 244 0x0dd1 ? pll control register...................... ............................... 244 0x0dd2 ? pll control register...................... ............................... 244 0x0dd3 ? pll control register...................... ............................... 244 0x0dd4 ? pll control register...................... ............................... 244 0x0dd5? pll control register....................... ............................... 245 0x0dd6? pll control register....................... ............................... 245 lcdc ? pll (memory clock).......................... ............................... 246 0x0dd8 ? pll control register...................... ............................... 246 0x0dd9 ? pll control register...................... ............................... 246 0x0dda? pll control register ....................... .............................. 246 0x0ddb? pll control register ....................... .............................. 246 0x0ddc? pll control register....................... .............................. 246 0x0ddd? pll control register....................... .............................. 247 0x0dde? pll control register ....................... .............................. 247 lcdc ? dac........................................ ........................................... 247 0x0de0? dac control register....................... .............................. 247 mcu................................................ .................................................. 2 48 0x0f00 ? spi flash mode control register........... ....................... 248 0x0f01 ? mcu clock control register ................ ......................... 248 0x0f02 ? spi clock control register................ ............................ 248 0x0f03 ? dma control register...................... .............................. 249 0x0f04 ? flash busy control register............... ........................... 249 0x0f05 ? wait control register..................... ................................. 249 0x0f06 ? dma page register ......................... .............................. 249 0x0f07 ? dma index register........................ ............................... 249 0x0f08 ? dma length mid byte register.............. ....................... 249 0x0f09 ? dma length low byte register.............. ...................... 250 0x0f0a ? dma command buffer1 register.............. .................. 250 0x0f0b ? dma command buffer2 register.............. .................. 250 0x0f0c ? dma command buffer3 register.............. .................. 250 0x0f0d ? dma command buffer4 register.............. .................. 250 0x0f0e ? dma command buffer5 register.............. .................. 250 0x0f0f ? clock switch wait control register........ ...................... 250 0x0f10 ? dma read/write buffer1 register........... ..................... 250 0x0f11 ? dma read/write buffer2 register........... ..................... 250 0x0f12 ? dma read/write buffer3 register........... ..................... 250 0x0f13 ? dma read/write buffer4 register........... ..................... 251 0x0f14 ? dma read/write buffer5 register........... ..................... 251 0x0f15 ? dma read/write buffer6 register........... ..................... 251 0x0f16 ? dma read/write buffer7 register........... ..................... 251 0x0f17 ? dma read/write buffer8 register........... ..................... 251 0x0f18 ? spi flash status command register ......... ................. 251 0x0f19 ? spi flash busy control register........... ........................ 251 0x0f1a ? dma length high byte register............. ...................... 251 0x0f20 ? mcu control register...................... .............................. 252 0x0f21 ? isp passcode register..................... ............................. 252 0x0f22 ? timer0 divider high byte register......... ....................... 252 0x0f23 ? timer0 divider low byte register.......... ....................... 252 0x0f24 ? timer1 divider high byte register......... ....................... 252 0x0f25 ? timer1 divider low byte register.......... ....................... 252 0x0f26 ? timer2 divider high byte register......... ....................... 252 0x0f27 ? timer2 divider low byte register.......... ....................... 252 0x0f28 ? timer3 divider high byte register......... ....................... 253 0x0f29 ? timer3 divider low byte register.......... ....................... 253 0x0f2a ? timer4 divider high byte register ......... ...................... 253 0x0f2b ? timer4 divider low byte register.......... ...................... 253 0x0f2c ? osd dma busy check delay register ......... ............. 253 mcu sfr register................................... ....................................... 253 0x9a ? code bank address register.................. .......................... 253 0xfa ? interrupt7~14 control register............. ............................ 253 0xfb ? interrupt7~14 control register............. ............................ 253 0xfc ? interrupt7~14 control register............. ............................ 253 0xfd ? interrupt7~14 control register............. ............................ 254 0xfe ? interrupt7~14 control register............. ............................ 254 0xe2 ? cache control register..................... ................................ 254 interrupt vector address.......................... ....................................... 254 0x80 ? sfr register............................... ....................................... 254 TW8823 ? tft flat panel controller techwell, inc. 9 rev a 11/20/2009 0x81 ? sfr register............................... ........................................254 0x82 ? sfr register............................... ........................................254 0x83 ? sfr register............................... ........................................254 0x84 ? sfr register............................... ........................................255 0x85 ? sfr register............................... ........................................255 0x86 ? sfr register............................... ........................................255 0x87 ? sfr register............................... ........................................255 0x88 ? sfr register............................... ........................................255 0x89 ? sfr register............................... ........................................255 0x8a ? sfr register ............................... .......................................255 0x8b ? sfr register ................................ .......................................255 0x8c ? sfr register............................... .......................................255 0x8d ? sfr register................................ .......................................255 0x8e ? sfr register ................................ .......................................256 0x90 ? sfr register............................... ........................................256 0x91 ? sfr register............................... ........................................256 0x92 ? sfr register............................... ........................................256 0x93 ? sfr register................................ ........................................256 0x95 ? sfr register................................ ........................................256 0x98 ? sfr register................................ ........................................256 0x99 ? sfr register............................... ........................................256 0xa0 ? sfr register ............................... .......................................256 0xa8 ? sfr register ............................... .......................................256 0xb0 ? sfr register ............................... .......................................256 0xb8 ? sfr register ............................... .......................................257 0xc0 ? sfr register............................... .......................................257 0xc1 ? sfr register............................... .......................................257 0xc2 ? sfr register............................... .......................................257 0xc3 ? sfr register............................... ....................................... 257 0xc4 ? sfr register............................... ....................................... 257 0xc5 ? sfr register............................... ....................................... 257 0xc6 ? sfr register............................... ....................................... 257 0xc7 ? sfr register............................... ....................................... 257 0xc8 ? sfr register............................... ....................................... 257 0xc9 ? sfr register............................... ....................................... 258 0xca ? sfr register................................ ...................................... 258 0xcb ? sfr register................................ ...................................... 258 0xcc ? sfr register................................ ...................................... 258 0xcd ? sfr register................................ ...................................... 258 0xce ? sfr register................................ ...................................... 258 0xd0 ? sfr register............................... ....................................... 258 0xd8 ? sfr register............................... ....................................... 258 0xe0 ? sfr register............................... ....................................... 258 0xe8 ? sfr register................................ ....................................... 258 0xe9 ? sfr register............................... ....................................... 259 0xea ? sfr register............................... ...................................... 259 0xeb ? sfr register............................... ...................................... 259 0xf0 ? sfr register............................... ....................................... 259 0xf8 ? sfr register............................... ....................................... 259 0xf9 ? sfr register............................... ....................................... 259 copyright notice................................... ....................................... 260 trademark acknowledgment ........................... ......................... 260 disclaimer......................................... ............................................ 260 life support policy................................ ...................................... 260 revision history................................... ............................................. 260 TW8823 ? tft flat panel controller techwell, inc. 10 rev a 11/20/2009 introduction applications in-car display controller portable dvd and dvrs players portable media player description the TW8823 incorporates many of the features requir ed to create multi-purpose in-car lcd display system in a single package. it integrates a high quality 3d comb ntsc/pal/secam video decoder, triple high speed rgb adcs, high quality scaler, bit-mapped osd, triple d acs and images enhancement functions which include black an d white stretch, favorite color enhancement and etc. it also supports panoramic scaling for conversion to wide s creen display. on the input side, it supports a rich comb ination of cvbs, s-video, analog rgb as well as digital ycbcr/ rgb inputs. on the output side, it supports both digita l and analog panel type with its built-in timing controller and analog rgb output. it also support lvds type panel. TW8823 also has two pips (picture in picture) funct ion that can display three display sources simultaneously on one single window. it also has built-in bit-mapped osd with 16-bit color depth and acceleration function. it can also accept 18- bit external osd input. in addition, TW8823 has bui lt-in high performance microcontroller with cache. its spi int erface supports various serial flash types. analog video decoder ? ntsc (m, 4.34) and pal (b, d, g, h, i, m, n, n combination), pal (60), secam with automatic format detection ? two 10-bit adcs and analog clamping circuit. ? fully programmable static gain or automatic gain co ntrol for the y or cvbs channel ? programmable white peak control for the y or cvbs channel ? software selectable analog inputs allows either co mposite or s-video input ? high quality motion adaptive 3d comb filter for bo th ntsc and pal with concurrent 3d noise reduction ? pal delay line for color phase error correction ? image enhancement with 2d dynamic peaking and cti. ? digital sub-carrier pll for accurate color decodin g ? digital horizontal pll and advanced synchronizatio n processing for vcr playback and weak signal performance. ? programmable hue, brightness, saturation, contrast , sharpness. ? high quality horizontal and vertical filtered down scaling with arbitrary scale down ratio ? detection of level of copy protection according to macrovision standard analog rgb inputs ? triple high speed 10-bit adcs with clamping and programmable gain amplifier. ? sog and h/v sync support for ypbpr or rgb input ? built-in line locked pll with sync separator ? support analog input resolution up to 1080i or wxg a dual digital inputs support ? dual channel digital inputs support with following combination: o 1 channel 18/16-bits inputs and 1 channel 8-bits inputs o 1 channel 24 bits digital rgb/ycbcr inputs ? support both 656 and 601 video formats ? allows connection to external hdmi receiver built-in microcontroller ? built-in 8052 mcu up to 72mhz clock ? built-in code cache memory to enhance cpu performance. ? support single/dual/quad io spi flash ? system programming through uart ? support spi dma read/write to osd memory ? support i2c master interface with gpio ? support two uart interface up to 115200bps TW8823 ? tft flat panel controller techwell, inc. 11 rev a 11/20/2009 ? support ir receiver and interrupt output tft panel support ? built-in both analog and digital timing controller with programmability. ? supports optional single channel lvds panel with resolution up to wxga, 80mhz ? supports 3, 4, 6 or 8 bits per pixel up to 16.8 mi llion colors with built-in dithering engine ? support analog panel with resolution up to wqvga, 20mhz on screen display ? supports three window bitmapped osd, one 16 bits an d two 8 bits bitmap osd. ? built-in osd controller with bit blit engine ? supports variety functions included like blinking, transparency and blending. ? supports external osd with external alpha blending control. ? support osd compression image processing ? high quality scaler with both up/down and nonlinea r scaling support ? built-in 2d de-interlacing function ? programmable hue, brightness, saturation, contrast ? sharpness control with vertical peaking up to +12d b ? programmable color transient improvement control ? supports programmable cropping of input video and graphics. ? independent rgb gain and offset controls ? panorama / water-glass scaling ? dtv hue adjustment ? programmable 10-bit gamma correction for each colo r ? operated in frame sync mode only ? black/white stretch ? programmable favorite color enhancement pip function ? two independent pips ? variable sub window size ? pop with alpha blending ? support both 16-bit ypbpr and rgb data format ? built-in high quality up and down scaling engine f or pip ddr-sdram ? support 16 bits 155mhz ddr-sdram up to 256 mb host interface ? supports 2-wire serial bus interface ? supports 8-bits parallel host interface clock generation ? frequency synthesizer with spread spectrum generat e ddr memory and display clocks ? spread spectrum profile based on triangular modula tion with center spread ? modulation frequency and spread width can be selec table power management ? supports panel power sequencing. ? supports dpms for monitor power management. ? 1.8 / 2.5v / 3.3 v operation miscellaneous ? built-in single ccfl back light controller ? built-in single led back light controller ? built-in touch screen controller with 12-bit adc ? lvr, provides 100~200 msec. low voltage reset ? power-down mode ? single 27mhz crystal ? 216-pin lqfp package TW8823 ? tft flat panel controller techwell, inc. 12 rev a 11/20/2009 order information package description part # name description pin count body size lqfp 216 low profile quad flat package 216 24 x 24 mm^2 TW8823 ? tft flat panel controller techwell, inc. 13 rev a 11/20/2009 TW8823 flat panel tv/monitor controller functional block diagram rin0, 1 gin0,1 bin0,1 3d - comb video decoder lvds image enhance ddr controller input measurement pip2 pip1 dtv 2 i/f dtv 1 i/f rgb adc 16 - bit osd mixer output formatter tcon dac 2 - wire serial bus mcu main scaler timing generator spi parallel host-bus yin0~3 dtvclk dtvd[23:0] dtvhs, vs dtvde yout lvds tcon signals rgb out flat panel out i2c_sdat i2c_sclk mcu port spi ddr cin 8 - bit osd TW8823 ? tft flat panel controller techwell, inc. 14 rev a 11/20/2009 TW8823 flat panel tv or tv + pc monitor system TW8823 ? tft flat panel controller techwell, inc. 15 rev a 11/20/2009 functional description overview techwell?s TW8823 flat panel tv/monitor controller is a highly integrated tft panel controller. it integrates a high quality 3d comb ntsc/pal/secam vi deo decoder, triple high speed rgb adc, single channel lvds, dual scalers for pips support, timing controller, triple dacs and flexible bit-mapped os d engine. this unique level of mixed signal integrati on turns a tft panel into a flexible display system . its built-in triple adcs and pll allow both ypbpr and r gb input support. separate flexible digital inputs interface also allow it to connect other front-end chips. it incorporates easy-to-operate and powerful features in a single package for multi-purpose in-c ar lcd display, portable dvd and dvrs media players . the TW8823 contains all the logic required to conve rt standard tv, dtv, and pc monitor signals to the digital control and data signals required to drive various tft panel types. it supports lvds panel resolutions up to wxga(1366x768), 80mhz, as well as analog tft panel resolutions up to wqvga(480 x 234), 20mhz. the chip accepts cvbs (composite) analog input or s -video analog input or analog rgb input for use as a video monitor and up to 11 analog inputs can be c onnected simultaneously.. the integrated analog front-end contains total five adcs with clamping circuits and automatic gain control (agc) circuit on certain channel to minimi ze external component count. it employs proprietary 3d comb filter y/c processing technologies to produce exceptionally high quality pictures. TW8823 has three high speed adcs that can support v arious analog signal inputs up to 1080i or wxga. the chip's internal logic synchronizes the panel fr ame rate to the incoming input frame rate. a high q uality image-scaling engine is used to convert the lower r esolution formats or high resolution dtv formats to the output panel resolution. an internal de-interlacing engine also allows interlaced video to be supporte d. on screen display is supported through either exter nal osd chip or on-chip osd for maximum flexibility . the TW8823 also accepts a 24 bit digital rgb input from external hdmi tm receiver or adcs. in addition, it accepts 8/16/24 bits digital ycbcr input. the TW8823 has a built-in lvds transmitter for dire ct connecting with various lcd panel. for the varie ty for usage, TW8823 has a built-in tcon for direct co nnecting with low cost tcon-less panel. the TW8823 also supports tft panel power sequencing , dpms (vesatm display power management signaling) signaling and power management. it also has built-in single channel ccfl or led back light controller to further simplify the system design. b esides, built-in touch screen controller in TW8823 can provides accurate position reading with simplified digital operation and can also be used to monitor u p to four auxiliary analog inputs. the control interface supports both a 2-wire serial bus interface and 8b it parallel interface. in addition, TW8823 has built-i n high performance microcontroller with cache, and its spi interface supports various serial flash types. the TW8823 core operates at 1.8 v, the io at 2.5v a nd 3.3 v. TW8823 packaged in a 216-pin lqfp package. analog front-end the analog front-end converts analog video signals to the required digital format. there are five anal og front-end channels. two channels are dedicated to a nalog video support. every channel contains analog anti-aliasing filter, clamping circuit and 10-bit a dcs. it allows the support of cvbs, s-video input s ignals for main or sub display. the other three channels a re dedicated to ypbpr component video or rgb input support. every channel contains the analog clamping circuit, variable gain amplifier and adcs. it allo ws three separate inputs to be connected simultaneousl y. a built-in line locked pll is used to generate t he sampling clock for various inputs. TW8823 ? tft flat panel controller techwell, inc. 16 rev a 11/20/2009 video source selection TW8823 has total 11 analog inputs for maximum flexi bility. of the 11 inputs, 6 are used for 2 channels of ypbpr/rgb input with corresponding sog pin. the oth er 5 inputs are used by video decoder to allow up to 4 cvbs or 1 s-video input. all inputs are softwa re selectable. clamping and automatic gain control all five channels have built-in clamping circuit th at restores the signal dc level. the y channel rest ores the back porch of the digitized video to a programmable level. the c channel restores the back porch of th e digitized video to a level of 128. the r, g, and b channels restore the blank to a level of 16. this o peration is automatic through internal feedback loop. in the case of rgb channel, two clamping modes are provided. when the input is ypbpr signal, the clamping to pre-determined dc level is done through internal feedback loop. when the input is pc rgb signal, the input is self clamped to the zero level . the automatic gain control (agc) of the y channel a djusts input gain so that the sync tip is at a desi red level. the white peak protection logic is included to prevent saturation in the case of abnormal propo rtion between sync and white peak level. TW8823 ? tft flat panel controller techwell, inc. 17 rev a 11/20/2009 video decoder sync processor TW8823 has two sync processors, one for rgb channel and one for video channel. the sync processor of video input detects horizontal synchronization a nd vertical synchronization signals in the composit e video or in the y signal of an s-video signal. the processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection i n stable signal as well as in unstable signals such as those from vcr fast forward or backward. horizontal sync processing the horizontal synchronization processing contains a sync separator, a phase-locked-loop (pll), and th e related decision logic. the horizontal pll locks onto the extracted horizon tal sync in all conditions to provide jitter free i mage output. from there, the pll also provides orthogona l sampling raster for the down stream processor. it has wide lock-in range for tracking any non-standar d video signal. vertical sync processing the vertical sync separator detects the vertical sy nchronization pattern in the input video signals. a detection window controls the determination of sync . this provides more reliable synchronization. it simulates the functionality of a pll without the co mplexity of a pll. the field status is determined a t vertical synchronization time based on the vertical and horizontal sync relationship. color decoding y/c separation the color-decoding block contains the luma / chroma separation for the composite video signal and mult i- standard color demodulation. for ntsc and pal stand ard signals, the luma / chroma separation can be done either by comb filter or notch/band-pass filte r combination. for secam standard signals, only notch/band-pass filter is available. the default se lection for ntsc/pal is comb filter. the characteri stics of the band-pass filter can be found in the filter cur ve section. in the case of comb filter, the TW8823 separates lu ma (y) and chroma (c) of a ntsc/pal composite video signal using a proprietary 3d/2d adaptive com b filter. this technique leads to good y/c separati on with small cross luma and cross color at both horiz ontal and vertical edges. due to the line buffer us ed in the comb filter, there is always two lines processi ng delay in the output images no matter what standa rd or filter option is chosen. color demodulation the color demodulation for ntsc and pal standard is done by quadrature mixing the chroma signal to the base band and extracting the chroma components with low-pass filter. the low-pass filter characteristic can be selected for optimized transi ent color performance. for the pal system, the pal id or the burst phase switching is identified to aid t he pal color demodulation. the secam color demodulation process consists of be ll filtering, fm demodulator and de-emphasis filtering. the chroma carrier frequency is identifi ed in the process and used to control the secam col or demodulation. the sub-carrier signal for use in the color demodul ator is generated by direct digital synthesis pll t hat locks onto the input sub-carrier reference (color b urst). this arrangement allows any sub-standard of ntsc and pal to be demodulated easily. automatic chroma gain control the automatic chroma gain control (acc) compensates for reduced amplitudes caused by transmission loss in video signal. in the ntsc/pal standard, the color reference signal is the burst on the back po rch. this color-burst amplitude is calculated and compar ed to standard amplitude. the chroma (cx) signals a re then compensated in amplitude accordingly. the rang e of acc control is ?6db to +24db. TW8823 ? tft flat panel controller techwell, inc. 18 rev a 11/20/2009 low color detection and removal for low color amplitude signals, black and white vi deo, or very noisy signals, the color will be ?kill ed?. the color killer uses the burst amplitude measurement t o switch-off the color when the measured burst amplitude falls below a programmed threshold. the t hreshold has programmed hysteresis to prevent oscillation of the color killer operation. this fun ction can be disabled by programming a low threshol d value. automatic standard detection the TW8823 has build-in automatic standard discrimi nation circuitry. the circuit uses burst-phase, bur st- frequency and frame rate to identify ntsc, pal or s ecam color signals. the standards that can be identified are ntsc (m), ntsc (4.43), pal (b, d, g, h, i), pal (m), pal (n), pal (60) and secam (m). each standard can be included or excluded in the st andard recognition process by software control. the identified standard is indicated by the standard se lection (sdt) register. automatic standard detectio n can be overridden by software controlled standard s election. video format support TW8823 supports all common video formats as shown i n table 1. the video decoder needs to be programmed appropriately for each of the composite video input formats. table 1. video input formats supp orted by the TW8823 format lines fields fsc country ntsc-m 525 60 3.58 mhz u.s., many others ntsc-japan (1) 525 60 3.58 mhz japan pal-b, g, n 625 50 4.43 mhz many pal-d 625 50 4.43 mhz china pal-h 625 50 4.43 mhz belgium pal-i 625 50 4.43 mhz great britain, others pal-m 525 60 3.58 mhz brazil pal-cn 625 50 3.58 mhz argentina secam 625 50 4.406mhz 4.250mhz france, eastern europe, middle east, russia pal-60 525 60 4.43 mhz china ntsc (4.43) 525 60 4.43 mhz transcoding notes: (1). ntsc-japan has 0 ire setup. component processing luminance processing the TW8823 decoder adjusts brightness by adding a p rogrammable value (in register brightness) to the y signal. it adjusts the picture contrast by c hanging the gain (in register contrast) of the y si gnal. the TW8823 decoder also provides a sharpness contro l function through a control register. the center frequency of the peaking filter is selectable. a co ring function is provided along with the sharpness control to reduce enhancement to the noise. TW8823 ? tft flat panel controller techwell, inc. 19 rev a 11/20/2009 the hue and saturation when decoding ntsc signals, TW8823 decoder can adju st the hue of the chroma signal. the hue is defined as a phase shift of the subcarrier with res pect to the burst. this phase shift can be programm ed through a control register. the color saturation can be adjusted by changing th e gain of cb and cr signals for all ntsc, pal and secam formats. the cb and cr gain can be adjusted i ndependently for flexibility. analog rgb / ypbpr processor analog front-end this input path has three adcs to support analog rg b input or ypbpr input. the built-in clamping circu it works based on the mode selected. every channel inc ludes variable gain amplifier for gain adjustment. both gain and offset can be adjusted for flexibilit y. two software selectable inputs are available for each channel to allow two inputs to be connected simulta neously. both separated h/v sync and sync-on-green are supported. sync processor the sync processor for the rgb channel either takes the separated h/v sync input or separates the composite sync input from one of the sog inputs int o h/v sync for driving the on-chip sampling pll. it contains necessary logics to detect and bypass irre gular syncs. the on-chip pll has sub-phase control to enable accurate sampling timing. component processor there are built-in color space converter and tint c ontrol logic for the ypbpr input. during ypbpr component input operation, luminance contrast and b rightness as well as pb / pr saturation can be controlled by registers. in the case of rgb mode, t he gain and offset of rgb can also be digitally controlled. touch screen controller built-in 12-bit adc touch screen controller in tw88 23 provides accurate position reading with simplifi ed digital operation and can also be used to monitor u p to four auxiliary inputs with touch interrupt. digital input support in addition to analog inputs, the TW8823 has dual d igital inputs mode for ycbcr or rgb data. the combination could be either one channel 18/16-bit a nd one channel 8-bit at dual digital input mode or a single 24-bit digital inputs mode. the input includ es vsync, hsync, pixel clock and the optional data qualifier. for interlaced video, the timing relatio nship between vsync and hsync determine the field flag. the optional data qualifier is needed when in put video data is not continuously valid within a l ine. for the ycbcr mode, TW8823 can support 8-bit 656 as wel l as 8/16-bit 601 modes. the 656 interface supports both interlaced and progressive standard. TW8823 ? tft flat panel controller techwell, inc. 20 rev a 11/20/2009 tft panel support the TW8823 supports varieties of active matrix tft panels including lvds panel resolutions up to wxga(1280x768), 80mhz, as well analog panel resolut ions up wqvga(480 x 234) , 20mhz. dithering if the color depth of the input data is larger than the lcd panel color depth, the TW8823 can be set t o dither the image. up to four bits of apparent color depth can be added with the internal dithering abi lity of the TW8823. this allows lcd panels with 4, 6 or 8 b its per color per pixel to display up to 16.8 milli on colors and lcd panels with 3 bits per color per pix el to can display up to 2.1 million colors. the TW8823 has both spatial and frame modulation di thering. when dithering with the least significant 4- bits of input data the TW8823 uses spatial modulati on with 4x4 blocks of pixels. when dithering with t he least significant 1 to 3 bits of input data, the tw 8823 uses either spatial modulation with 2x2 pixel blocks, or frame modulation. lvds out put format TW8823 is able to control output order for panel co ntrol signal that vs, hs and de. TW8823 ? tft flat panel controller techwell, inc. 21 rev a 11/20/2009 lvds color mapping TW8823 is able to control output color order. TW8823 ? tft flat panel controller techwell, inc. 22 rev a 11/20/2009 image control input image control the input cropping control provides a way for progr amming the active display window region for the selected input video or graphic. in the normal oper ation, the first active line starts with the vsync signal. this and vertical active length register setting ar e used to determine the active vertical window. the active pixel starts hsync. this and the horizontal active width register are used to determine the active horizontal window. the vertical window is programme d in line increments. the horizontal window is programmed in one pixel increments for single pixel input mode or two pixels increments for double pix els input mode. if data qualifier is used, then only qu alified pixels will be counted in the window size. image scaling the TW8823 internal image-scaling engine operates i n several modes. the first is the bypass mode. no image scaling is done in this mode. the number of a ctive output lines per frame and the number of acti ve output pixels per line are identical to the input a ctive lines and pixels, respectively. this mode is best used for displaying computer graphic at panel's native r esolution. by default, the input active window is zoomed up to the full screen for display. this is used for non- interlaced data like pc graphics or progressive sca n video. the vertical and horizontal magnification ratio can be adjusted independently. TW8823 has frame-syn c mode which does not use frame buffer. in this mode, the zoom ratio and output clock rate should b e coordinated appropriately to avoid internal buffe r overrun. the TW8823 has a de-interlacing mode to process int erlaced video inputs. in this mode, every input fie ld is zoomed to the full output frame resolution. the de-interlaced fields can also be properly compensat ed to have fields aligned correctly to avoid any artifact s. the offset can be programmed to provide maximum flexibility. the horizontal scaler can be programmed to perform non-linear scaling : panorama scaling for displayin g 4:3 input on a 16:9 display and water-glass scaling for displaying 16:9 input on a 4:3 display. image enhancement processing adaptive black/white stretch this feature is to expand dynamic range of the inpu t image, which creates more vivid image impression. favorite color enhancement TW8823 provides three independent color enhancement s. the center axis of each color can be adjusted over a 360 degrees range provided none of those two are overlapped. the range and the amount of enhancement can also be independently adjusted. TW8823 ? tft flat panel controller techwell, inc. 23 rev a 11/20/2009 picture-in-picture double window / picture-in-picture (pip) TW8823 can display two live pictures on a single di splay. in the case of what we called pip, small siz e of sub-window can be displayed over full size of main- window. the frame (outline of window) can be added with cho ice of color and width. example of double window modes pip alpha blending pip image can be used as an osd type overlay graphi cs. user can specify specific color as a ?key color ? which disabling overlaying and showing behind main image. where pip and main image are overlaid, user can define blending ratio (alpha1). and also c an define blending ratio of main image with black c olor (alpha2) as a dimming function. [usage] - enable pip alpha blending (0x8280[7] = 1). enable 565 mode (0x8280[6] = 1) as well, if it is preferr ed. - set ?key color? center level by using rkey (0x828 2), gkey (0x8283) and bkey (0x8284). also set ?key range? (0x0685~0x0687) for the ?key color? deviatio n from its center setting. - turn on ?key position display? mode if you want t o make sure the area detected as ?keyed?. - adjust alpha1 (0x8280[4:0]) and alpha2 (0x8281[4: 0]). main sub main sub TW8823 ? tft flat panel controller techwell, inc. 24 rev a 11/20/2009 [limitations] - when 565 mode, color depth is limited and may sho w steps on original gradation. - when 565 mode, try to choose color of input image which truncated portion (lsb 2 bit will be truncat ed in y, lsb 3 bit in cb and cr) has about middle valu e (if 3 bit is truncated, these portion better have value of around 3 or 4) to avoid input level translated i nto 2 different output level due to noise. (if inpu t is digital signal, this situation may be avoidable.) key color gui menu main image gui menu pip image blending pip and main dimming is available as an option TW8823 ? tft flat panel controller techwell, inc. 25 rev a 11/20/2009 display timing the TW8823 is operated in frame sync mode only with no external memory required. in this mode, the output frame rate is synchronized with the input fr ame rate. since there is no frame buffer, the displ ay clock frequency and zoom ratio have to be properly selected to match the panel resolution. the interna l scaling engine absorbs the difference between the i nput line rate and output line rate as well as the difference between the input pixel rate and output pixel rate. the frequency of the flat panel clock output pin ca n be controlled by an internal frequency synthesize r. it also has spread spectrum function to reduce emi. the frequency equation of the flat panel clock output signal is described in the register section. external ddr sdram interface TW8823 uses a unified external ddr sdram for variou s functions, such as bit-mapped osd, 3d comb, 3d noise reduction and pip. the memory controller o f the TW8823 supports 16bit data width. the memory capacity can be up to 256 mbytes. when the chip is powered up, the cpu is responsible for setting all the on-chip configuration register s for ddr memory configuration. once the registers are se t, the cpu releases the software reset signal, then the ddr memory controller initializes the ddr memor y configuration using the parameters in the registers. after the initialization is done, the dd r memory is ready for use. the memory controller do es the memory refresh automatically. fphs fpde fpr/g/b0 fpr/g/b1 fpclk fphs fpde fpvs flat panel output signals TW8823 ? tft flat panel controller techwell, inc. 26 rev a 11/20/2009 on screen display TW8823 osd controller supports bitmap with 8/16 bit -per-pixel mode up to 3 windows, one 16-bits and two 8-bits mode. between 8-bits and 16-bits windows , color could be blended by osd alpha blending controller. the powerful bit-blit engine makes your system more fancier. any pixel in an 8 bit osd window can be assigned any one of 256 user-defined true colors through a 256 x 32 bits look-up-table. two look-up-tables are available; one for each 8 bi t osd window. the bitmap is loaded into external sdram by mcu wri te operation or osd block fill operation. user can define the displayed pixel colors on a pixel by pix el basis. the pixels can be represented using eithe r 8- bits or 16-bits per pixel. alpha blending can be on either per pixel based or per window based. the maximum bitmapped image size depends on panel resol ution and sdram size. . external osd port a dedicated port is provided for an external osd co ntroller. the TW8823 provides the hsync, vsync and dot clock signals, and external osd controller provides a 18 bits color data values together with valid data indicator (6 bits for each r, g and b color). it's compatible with popular osd controllers from renesas (mitsubishi) and other companies. in case of 18 bit osd data reception, color palette is not used and 18 bit data represents 262144 colo r space directly. external osd port share with mcu gp io ports and dtv input ports. TW8823 ? tft flat panel controller techwell, inc. 27 rev a 11/20/2009 osd display and image in memory the TW8823 osd provides a flexible mapping between its display on the lcd and its image stored in the memory. in general a working space in the memory i s defined for each window. the working space is mu ch larger than the display size of the window. multip le images can be stored in a working space. pointe rs are provided to point to the starting location of the i mage to be displayed. animation can be achieved by changing the pointers during the vertical blanking times. window display starting location and sizes there are four registers used to specify the starin g location and size on the lcd: window i horizontal start window i vertical start window i horizontal length window i vertical length TW8823 ? tft flat panel controller techwell, inc. 28 rev a 11/20/2009 window working space three registers together define the working space s tarting location and boundaries: window i buffer memory starting address window i buffer memory horizontal length window i buffer memory vertical length two registers point to the starting location of the image stored: window i image vertical start window i image horizontal start the above registers are per window based. all horizontal length definitions are on per pixel base. the internal hardware takes into account 8-b it (one byte) or 16-bit (2 bytes) variation. different windows can share the same working space. TW8823 ? tft flat panel controller techwell, inc. 29 rev a 11/20/2009 osd display path two 8-bit windows, window 0 and window 1, are provi ded. each has its own look up table. when these two windows are overlapped, widow 0 has higher priority; i.e. the overlapped window 1 area will not show up on the lcd. the look up table maps the 8 bit value stored in th e memory to a 32 bits content, which consists of bl ink attribute, per pixel alpha value, and 24-bit rgb va lue. one 16-bit window is provided. it supports five di fferent formats: ycbcr422, ycbcr655, rgb565, rgb444 4, and rgb1555. a 16-bit pixel data fetched is converted to a 24-bi t rgb. the resulting 24-bit rgb data is blended wi th the 24-bit rgb from the 8-bit window if the 8-bit windo w is overlapped with the 16-bit window. the blende d osd pixel and alpha values are then stored in a line bu ffer. the line buffer is later shifted out to display. w hile it is shifting out the osd pixel data is blend ed with the incoming video data. TW8823 ? tft flat panel controller techwell, inc. 30 rev a 11/20/2009 osg operation i ? block fill in the simplest block fill operation, the data in t he block fill color register is repeatedly used to fill up the destination region. for more advanced block fill o peration, one can invoke the color conversion, sele ctive overwrite, and bitblt functios. to perform the block fill, set the following regist ers properly. osgmode (0x0700[7:6]) = 10 bexpm (0x0700[1:0]) = 00 rlc function enable (0x0704[0]) = 0 destination buffer memory starting address (0x0770 ~ 0x0772) destination buffer memory horizontal length (0x0773) transfer destination horizontal start (0x0774 ~ 0x0775) transfer destination vertical start (0x0776 ~ 0x0777) transfer horizontal length (0x0768 ~ 0x0769) transfer vertical length (0x076a ~ 0x076b) block fill color (0x070e ~ 0x070f) msksel (0x0700[5:4]) color_con (0x0700[3]) bpp (0x0700[2]) if any one of the functions, color conversion, sele ctive overwrite, bitblt, is selected, the additiona l register corresponding that function needs to be set properl y. to start the operation, write ?1? to op_start (0x0701[0]) while the block fill operation is in progress, the osg_stus (0x0701[7]) stays at ?1? until it is done. when the osg_stus returns to ?0?, write ?0? to op_start to conclude the operation. TW8823 ? tft flat panel controller techwell, inc. 31 rev a 11/20/2009 TW8823 ? tft flat panel controller techwell, inc. 32 rev a 11/20/2009 osg operation ii ? mcu/dma write the mcu/dma write operation provides the means to i mport an existing image to the osd. in addition to the color conversion, selective overwrite, and bitblt f unctions, one can invoke bit expansion, special 8 t o 16 bit expansion, and rlc decompression. the mcu write is carried out by writing data to the data port for mcu write register (0x0702), while t he dma write is carried out by spi dma tunnels its data to osd directly. either way the data is directed to a 64-byte fifo. as soon as the fifo is filled, the actual op eration commences. additional data is accepted whe n the fifo becomes empty. one must ensures that there ar e enough data to fill up the destination block area , defined by transfer vertical length and transfer ho rizontal length. to perform the mcu/dma write, set the following reg isters properly. osgmode (0x0700[7:6]) = 00 destination buffer memory starting address (0x0770 ~ 0x0772) destination buffer memory horizontal length (0x0773) transfer destination horizontal start (0x0774 ~ 0x0775) transfer destination vertical start (0x0776 ~ 0x0777) transfer horizontal length (0x0768 ~ 0x0769) transfer vertical length (0x076a ~ 0x076b) msksel (0x0700[5:4]) color_con (0x0700[3]) bpp (0x0700[2]) bexpm (0x0700[1:0]) sp8to16 (0x0703[4]) rlc function enable (0x0704[0]) if any one of the functions, color conversion, sele ctive overwrite, bitblt, bit expansion, special 8-t o-16 bit expansion, rlc decompression, is selected, the addi tional register corresponding that function needs t o be set properly. mcu write to start the mcu write operation, write ?1? to op_start (0x0701[0]). once this bit is set the osg_stus (0x0701[7]) becomes ?1?. write 64-byte data to data port for mcu write (0x0702) check the fifo_stus (0x0701[6]) wait till it becomes ?0?, then write the next 64-by te data. upon finishing the last byte data write, write ?1? to mcuwd (0x0701[1]) this makes the internal circuitry to fill up the de stination area if the destination area is not fully filled yet. check the osg_stus (0x0701[7]) if it becomes ?0?, write ?0? to both op_start (0x0701[0]) and mcuwd (0x0701[1]) to conclude the operation. dma write TW8823 ? tft flat panel controller techwell, inc. 33 rev a 11/20/2009 to start the dma write operation, write ?1? to both osd_hw (ox0703[6]) and op_start (0x0701[0]). (thereafter the osg_stus (0x0701[7]) would change to ?1?.) set up the spi dma to perform dma read spi data (re fer to mcu operation documents) upon the spi dma operation is done (refer to mcu do cument), check osg_stus (0x0701[7]) if it becomes ?0?, write ?0? to op_start (0x0701[0]) to conclude the operation. transfer destination v start transfer destination h start dbm (destination buffer memory) starting address[23:0] dbm horizontal length transfer h length transfer v length source fifo 64 bytes mcu/dma write rlc decompression original destination contents bitblit / selective overwrite bit expansion colo r conversion special 8 to16 bit expansion alpah blending TW8823 ? tft flat panel controller techwell, inc. 34 rev a 11/20/2009 osg operation iii ? block transfer block transfer is used to transfer a block (rectang ular shaped) of data from one place to another. fu nctional operations available during block transfer are colo r conversion, selective overwrite, and bitblt. the source block of data as well as the destination block of d ata are fetched and functionally operated. the res ultant block of data is then written back to the destinati on. to perform the block transfer, set the following re gisters properly. osgmode (0x0700[7:6]) = 01 bexpm (0x0700[1:0]) = 00 rlc function enable (0x0704[0]) = 0 source buffer memory starting address (0x0760 ~ 0x0762) source buffer memory horizontal length (0x0763) transfer source horizontal start (0x0764 ~ 0x0765) transfer source vertical start (0x0766 ~ 0x0767 destination buffer memory starting address (0x0770 ~ 0x0772) destination buffer memory horizontal length (0x0773) transfer destination horizontal start (0x0774 ~ 0x0775) transfer destination vertical start (0x0776 ~ 0x0777) transfer horizontal length (0x0768 ~ 0x0769) transfer vertical length (0x076a ~ 0x076b) msksel (0x0700[5:4]) color_con (0x0700[3]) bpp (0x0700[2]) if any one of the functions, color conversion, sele ctive overwrite or bitblt is selected, additional register(s) corresponding that function needs to be set properl y. block transfer to start the block transfer operation, write ?1? to op_start (0x0701[0]). check the osg_stus (0x0701[7]). if it becomes ?0?, write ?0? to op_start (0x0701[0]) to conclude the operation. TW8823 ? tft flat panel controller techwell, inc. 35 rev a 11/20/2009 TW8823 ? tft flat panel controller techwell, inc. 36 rev a 11/20/2009 osg operation iv ? linear block transfer linear block transfer is similar to block transfer except the source is accessed linearly in the memor y. on top of those functions available to block transfer, linear block transfer can have these additional fu nctional operations: rlc decompression, bit expansion, and s pecial 8 to 16 bit expansion. to perform the block transfer, set the following re gisters properly. osgmode (0x0700[7:6]) = 11 source buffer memory starting address (0x0760 ~ 0x0762) destination buffer memory starting address (0x0770 ~ 0x0772) destination buffer memory horizontal length (0x0773) transfer destination horizontal start (0x0774 ~ 0x0775) transfer destination vertical start (0x0776 ~ 0x0777) transfer horizontal length (0x0768 ~ 0x0769) transfer vertical length (0x076a ~ 0x076b) msksel (0x0700[5:4]) color_con (0x0700[3]) bpp (0x0700[2]) bexpm (0x0700[1:0]) rlc function enable (0x0704[0]) if any one of the functions, color conversion, sele ctive overwrite, bitblt, bit expansion, special 8-t o-16 bit expansion, rlc decompression, is selected, the addi tional register corresponding that function needs t o be set properly. linear block transfer to start the linear block transfer operation, write ?1? to op_start (0x0701[0]). check the osg_stus (0x0701[7]). if it becomes ?0?, write ?0? to op_start (0x0701[0]) to conclude the operation. TW8823 ? tft flat panel controller techwell, inc. 37 rev a 11/20/2009 color conversion related registers: color_con (0x0700[3]) color conversion source color (0x0740 ~ 0x0747) color conversion target color (0x0748 ~ 0x074f) function: each source data is compared against the four color conversion source color registers (0x0740 ~0x0747). if the source data matches one of the fo ur colors defined, the content of the corresponding color conversion target color register (0x0748 ~ 0x074f) replaces the source dat a for further processing. TW8823 ? tft flat panel controller techwell, inc. 38 rev a 11/20/2009 bitblt logic related registers: msksel (0x0700[5:4]) bitblt logic (0x070b) bitblt mask (0x070c ~ 0x070d) selective overwrite (0x0750 ~ 0x0757) function: bitblt logic is a bit wise operation. for a given bit position, the bits from each of mask data, dest ination data, and source data forms a triplet with the mask data bit as the msb and source data bit as the lsb, {mi, di, si}. the triplet together with the bitblt logic register content forms a truth table. each bit of bitblt l ogic is bonded with one of the eight combinations of the triplet: bbl[0] ~ {000}, bbl[1] ~ {001}, ? bbl[7] ~ {111}. the content of the bitblt logic register specifies the outcome of the bit wise combination logic operation of mask data, destination data, and source data. by changi ng the content of the bitblt logic register, variou s logic operations can be achieved. the mask data is selectable by msksel . bitblt mask register is one of the choices. mux bitblt logic register 8 {m 7 ,d 7 ,s 7 } mux {m 6 ,d 6 ,s 6 } mux {m 0 ,d 0 ,s 0 } mux {m 15 ,d 15 ,s 15 } mux {m 14 ,d 14 ,s 14 } mux {m 8 ,d 8 ,s 8 } m: mask word d: destination word s: source word m i d i s i y i 0 0 0 bbl[0] 0 0 1 bbl[1] 0 1 0 bbl[2] 0 1 1 bbl[3] 1 0 0 bbl[4] 1 0 1 bbl[5] 1 1 0 bbl[6] 1 1 1 bbl[7] bbl[7:0] y 7 y 0 y 6 y 15 y 14 y 8 m i d i s i y i 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 default bbl content mux bitblt logic register 8 {m 7 ,d 7 ,s 7 } mux {m 6 ,d 6 ,s 6 } mux {m 0 ,d 0 ,s 0 } mux {m 15 ,d 15 ,s 15 } mux {m 14 ,d 14 ,s 14 } mux {m 8 ,d 8 ,s 8 } m: mask word d: destination word s: source word m i d i s i y i 0 0 0 bbl[0] 0 0 1 bbl[1] 0 1 0 bbl[2] 0 1 1 bbl[3] 1 0 0 bbl[4] 1 0 1 bbl[5] 1 1 0 bbl[6] 1 1 1 bbl[7] bbl[7:0] y 7 y 0 y 6 y 15 y 14 y 8 m i d i s i y i 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 default bbl content TW8823 ? tft flat panel controller techwell, inc. 39 rev a 11/20/2009 selective overwrite related registers: msksel (0x0700[5:4]) = 00 bitblt logic (0x070b) = 1100_1010 selective overwrite (0x0750 ~ 0x0757) function: selective overwrite is a special case of the bitblt logic operations. destination data to be overwrit ten or kept unchanged are programmed in the selective overwrite registers. the msksel must be set to ?00?. with t he default content of the bitblt logic register (11001 010), the destination data is kept unchanged if it matches one of the four selective overwrite registers. if unmatched, the destination data is overwritten by the source data. if the bitblt logic is programmed with (10101100), the outcome becomes: the matched data is overwritte n while the unmatched is kept.. bit expansion related registers: bpp (0x0700[2]) bexpm (0x0700[1:0]) 8 bit color expansion table (0x0710 ~ 0x071f) 16 bit color expansion table (0x0720 ~ 0x073f) function: bit expansion is used to expand source data of one/ two/four bits to eight or sixteen bit data. the bp p determines the data after expansion is 8-bit or 16- bit. there are 16 entries for each table. the foll owing shows the relationship between the incoming bits an d the corresponding entries. one bit table entry # 0 0 1 1 two bit table entry # 00 0 01 1 10 2 11 3 four bit table entry # 0000 0 0001 1 0010 2 ? . 1111 15 TW8823 ? tft flat panel controller techwell, inc. 40 rev a 11/20/2009 special 8 to 16 bit expansion related registers: bpp (0x0700[2]) = 0 bexpm (0x0700[1:0]) = 11 sp8to16 (0x0703[4]) = 1 osg16form (0x0703[3:1]) 16 bit color expansion table (0x0720 ~ 0x073f) function: this special bit expansion is used to alpha blend t he destination data. the source 8-bit data is not a pixel data but an alpha blending value. the source pixel data used to blend with the destination pixel is a lways taken from the first entry (entry #0) of the 16 bit color expansion table . using the 8-bit source data as the alpha blending p arameter, the destination data is fetched and alpha blended with the first entry of the 16 bit color expansion table . the resultant data is then written back to the destination. TW8823 ? tft flat panel controller techwell, inc. 41 rev a 11/20/2009 microcontroller interface the TW8823 registers are accessed via 2-wire serial bus interface as well as parallel host interface. it operates as a slave device. two wire serial bus interface figure 1. definition of the serial bus interface b us start and stop figure 2. one complete register write sequence via the serial bus interface mc_sd a start condition stop condition mc_sclk mc_sclk device id (1-7) r/w index (1-8) data (1-8) mc_sda start condition stop condition ack ack ack TW8823 ? tft flat panel controller techwell, inc. 42 rev a 11/20/2009 figure 3. one complete register read sequence via t he serial bus interface the two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW8823 r egisters. mc_sclk is the serial clock and mc_sda is the data line. both lines are pulled high by res istors connected to vdd. ics communicate on the bus by pulling mc_sclk and mc_sda low through open drain o utputs. in normal operation the master generates all clock pulses, but control of the mc_s da line alternates back and forth between the maste r and the slave. for both read and write, each byte i s transferred msb first, and the data bit is valid whenever mc_sclk is high. the TW8823 is operated as a bus slave device. it ca n be programmed to respond to one of two 7-bit slave device addresses by tying the addrsel (serial interface address) pin ether to vdd or gnd (see table 2.). if the addrsel pin is tied to vdd, then the least significant bit of the 7-bit address is a ?1?. if the addrsel pin is tied to gnd then the least signi ficant bit of the 7-bit address is a ?0?. the most significant 6-bits are fixed. the 7-bit address fie ld is concatenated with the read/write control bit to form the first byte transferred during a new transfer. i f the read/write control bit is high the next byte will be read from the slave device. if it is low the next byte w ill be a write to the slave. when a bus master (the host microprocessor) drives mc_sda from high to low, whi le mc_sclk is high, this is defined to be a start condition (see figure 1.). all slaves on the bus l isten to determine when a start condition has been asserted. after a start condition, all slave devices listen f or the their device addresses. the host then sends a byte consisting of the 7-bit slave device id and the r/w bit. this is shown in figure 2. (for the TW8823, t he next byte is normally the index to the TW8823 regis ters and is a write to the TW8823 therefore the fir st r/w bit is normally low.) after transmitting the device address and the r/w b it, the master must release the mc_sda line while holding mc_sclk low, and wait for an acknowledgemen t from the slave. if the address matches the device address of a slave, the slave will respond b y driving the mc_sda line low to acknowledge the condition. the master will then continue with the n ext 8-bit transfer. if no device on the bus respond s, the master transmits a stop condition and ends the cycl e. notice that a successful transfer always include s nine clock pulses. to write to the internal register of the TW8823, th e master sends another 8-bits of data, the TW8823 loads this to the register pointed by the internal index register. the TW8823 will acknowledge the 8-b it data transfer and automatically increment the index in preparation for the next data. the master can d o multiple writes to the TW8823 if they are in ascend ing sequential order. after each 8-bit transfer the re-start condition mc_sclk device id (1-7) r/w index (1-8) mc_sda ack ack data (1-8) stop condition nack start condition device id (1-7) r/w ack TW8823 ? tft flat panel controller techwell, inc. 43 rev a 11/20/2009 TW8823 will acknowledge the receipt of the 8-bits w ith an acknowledge pulse. to end all transfers to t he TW8823 the host will issue a stop condition. serial bus interface 7-bit slave address read/write bit 1 0 0 0 1 addrsel 0 1=read 0=write table 2. TW8823 serial bus interface 7-bi t slave address and read write bit a TW8823 read cycle has two phases. the first phase is a write to the internal index register. the sec ond phase is the read from the data register. (see figu re 3). the host initiates the first phase by sendin g the start condition. it then sends the slave device id together with a 0 in the r/w bit position. the inde x is then sent followed by either a stop condition or a second start condition. the second phase starts wit h the second start condition. the master then resends the same slave device id with a 1 in the r/w bit posit ion to indicate a read. the slave will transfer the con tents of the desired register. the master remains i n control of the clock. after transferring eight bits , the slave releases and the master takes control o f the mc_sda line and acknowledges the receipt of data to the slave. to terminate the last transfer the mast er will issue a negative acknowledge (mc_sda is left h igh during a clock pulse) and issue a stop conditio n. serial serial serial serial bus bus bus bus interface timing interface timing interface timing interface timing table table table table parameter symbol min typ max units bus free time between stop and start t bf 740 - - ns mc_sda setup time t ssdat 74 - - n s mc_sda hold time t hsdat 50 - 900 ns setup time for start condition t ssta 370 - - ns setup time for stop condition t sstop 370 - - ns hold time for start condition t hsta 74 - - ns rise time for mc_sclk and mc_sda t r - - 300 ns serial bus interface timing stop start stop start mc_sda mc_sclk t bf t hsta t sstop t ssta t ssdat t r t f t hsdat data TW8823 ? tft flat panel controller techwell, inc. 44 rev a 11/20/2009 parallel host interface for 8bit micro processor 1) host = 0 < write-write operation > < write-read operation > min max unit 1 1 * ns 2 1 * ns 3 3 * ns 4 1 * ns 5 2.0 * register clock cycle 6 3 * ns 7 0 * ns 8 0.5 1.5 register clock cycle 9 0 10 ns TW8823 ? tft flat panel controller techwell, inc. 45 rev a 11/20/2009 < read-read operation > < read-write operation > min max unit 1 1 * ns 2 1 * ns 3 3 * ns 4 1 * ns 5 2.0 * register clock cycle 6 3 * ns 7 0 * ns 8 0.5 1.5 register clock cycle 9 0 10 ns 10 10 * ns TW8823 ? tft flat panel controller techwell, inc. 46 rev a 11/20/2009 2) host = 1 < write operation > < read operation > min max unit 1 1 * ns 2 * * * 3 * * * 4 1 * ns 5 2.0 * register clock cycle 6 3 * ns 7 0 * ns 8 0.5 1.5 register clock cycle 9 0 10 ns TW8823 ? tft flat panel controller techwell, inc. 47 rev a 11/20/2009 parallel host interface for 8bit micro processor figure 4. parallel interface mode1 timing diagram. (host = 0) figure 5. parallel interface mode2 timing diagram. (host =1) hal hcs hwrn hrd addre write addre read had[7:0] write read write read hale hwrn hrdn address read had[7:0] addres data hcs hwrn hrdn address write had[7:0] TW8823 ? tft flat panel controller techwell, inc. 48 rev a 11/20/2009 built-in microcontroller TW8823 has built-in 8052 microcontroller which core cache memory to enhance cpu performance. the features of TW8823 mcu are: ? built-in 8052 mcu up to 72mhz clock speed ? single/dual/quad io spi flash and spi flash ? support spi dma read/write. ? 1k bytes code cache and 3k byte xdata memery ? support 2 uarts up to 115200bps ? system programming through uart(internal boot rom) ? built-in 3 timer and 2 baudrate generator ? power save mode with internal 32khz ? support ir receiver and irq output ? gpio ? most of digital pins can be configured to g pio power management the TW8823 supports panel power sequencing. typical tft panels require different parts of the panel power to be applied in the right sequence to avoid premature damage to the panel. pins are provided to control the panel backlight generator, digital circ uitry and panel driver, separately. the TW8823 cont rols the power up and power down sequence for the lcd pa nels through firmware control. this gives flexibility to meet different panel requirements. gamma correction TW8823 has built-in independent rgb 10-bit gamma ra m for the purpose of table lookup gamma correction. TW8823 ? tft flat panel controller techwell, inc. 49 rev a 11/20/2009 memory configuration TW8823 has embedded ddr sdram controller. it accept s 3 different memory configurations as noted in table 6. TW8823 operates with sdram of 16bits data -bus. register ddr size (0x0c0b[2:0]) need to be set properly according to the arrangement of extern al sdram. for ntsc, 3d-comb and 3d-nr concurrent operation is available with at least one 16mbit sdram. for pal, 3d-nr is available with one 16mbit sdram b ut 3d-comb cannot be used. by using two 16mbit sdram for pal, either 3d-comb or 3d-nr is available . with 64mbit or bigger sdram, 3d-comb and 3d-nr concurrent operation is available for pal. table 3. available 3d-comb and 3d-nr operation for each memory configuration bconfig config. available operation for ntsc availa ble operation for pal 0 64mb x 1 3d-comb & 3d-nr concurrent operation 3d-comb & 3d-nr concurrent operation 1 128mb x 2 3d-comb & 3d-nr concurrent operation 3d-comb & 3d-nr concurrent operation 2 256mb x 1 and up 3d-comb & 3d-nr concurrent operation 3d-comb & 3d-nr concurrent operation you also need to consider sdram space for pip and o sd. memory map when 3d comb is enabled, 3d comb memory start addre ss is fixed to 000000h, and when 3d noise reduction is enabled, it will be allocated after 3d comb. size: 3d comb - ntsc: 1.25mb, pal:4mb 3d noise reduction - ntsc: 640kb, pal:768kb bitmap osd memory start address = osd window0 memor y start address (0x0789:0x078a:0x078b) * 4 byte (unit). bitmap osd memory size = depend on the bitmap data size. virtual horizontal memory width is programmable. pip memory start address = pip base address (0x060e :0x060f:0x0610) * 4 byte (unit) pip memory size = window write width (0x0611[2:0], 0x0612) * window write height (0x0613[1:0], 0x0614) * 2byte * 2 frame. pip2 memory start address = pip2 base address (0x06 3e:0x063f:0x0640) * 4 byte(unit) pip2 memory size = window write width (0x0641[2:0], 0x0642) * window write height (0x0643[1:0], 0x0644). TW8823 ? tft flat panel controller techwell, inc. 50 rev a 11/20/2009 memory interface TW8823 supports external sdram for various function s including bit-mapped osd, 3d comb, 3d noise reduction and pip that require memory buffer. the m emory controller of the TW8823 supports 16bit data width up to 155 mhz clock rate. when power is up, it is reset by the internal reset signal and wait for the initial memory- timing per iod. to configuration of the sdram internal register memory controller performs initial cycle. after all initi al cycles performed, memory controller does the normal operat ion. the memory controller performs arbitration, access timing generation and refresh and configurat ion. test modes the test1 input pin provides test mode selection. i f this pin is low at the rising edge of the reset# pin and remains low, the TW8823 is in its normal operat ing mode. table 3 shows the other test modes made available with this pin. table 4 test modes test mode test1 before reset# rising edge test1 after reset# rising edge description normal 0 0 normal operation output tri-state 0 1 in this mode, all pin output d rivers are tri-stated. pin leakage current parameters can be measured. outputs high 1 0 in this mode, all pin output drive rs are forced to the high output state. v oh and i oh can be measured. outputs low 1 1 in this mode, all pin output driver s are forced to the low output state. v ol and i ol can be measured. TW8823 ? tft flat panel controller techwell, inc. 51 rev a 11/20/2009 pin diagram vss33 dtvd11/dtvb3/gpio51 dtvb2/p3.3/gpio50 dtvd10/dtvg7/gpio47 dtvd9/dtvg6/gpio46 dtvd8/dtvg5/gpio45 dtvd7/dtvg4/gpio44 dtvd6/dtvg3/gpio43 dtvd5/dtvg2/gpio42 dtvd4/dtvr7/gpio41 dtvd3/dtvr6/gpio40 dtvd2/dtvr5/gpio37 dtvd1/dtvr4/gpio36 dtvd0/dtv r 3/gpio35 dtvr2/to(p3.4)/gpio34 i2c_ssdat/gpio33 i2c_ssclk/gpio32 irq-out/gpio31/(b:boot_sel/host) test reset power_dn ddr_vss18 ddr_vdd18 ddr_vssp ddr_adr4 ddr_adr5 ddr_adr6 ddr_adr7 ddr_adr8 ddr_adr9 ddr_adr11 ddr_adr12 ddr_vddp ddr_udm ddr_data8 ddr_data9 ddr_data10 ddr_data11 ddr_vssp ddr_data12 ddr_data13 ddr_data14 ddr_data15 ddr_dqs1 ddr_vddp ddr_vssref ddr_vref(1.25v) dll_vss18(dll) dll_vdd18(dll) ddr_vssref ddr_clkn ddr_clk ddr_cke ddr_vddp vdda(r,g,b) alvss alvdd sog llvdd llvss ssvdd ssvss hadc hs/gpio93 hadc vs/gpio92 vss18 vdd18 hwait/osdb7/txd1/(p3.7)/gpio91 hale/osdb6/rxd1(p3.6)/gpio90 hwrl/osdb5/int07(p1.7)/gpio87 hrdl/osdb4/int06(p1.6)/gpio86 had7/osdg7/int05(p1.5)/gpio85 had6/osdg6/int04(p1.4)/gpio84 had5/osdg5/int03(p1.3)/gpio83 had4/osdg4/int02(p1.2)/gpio82 had3/osdr7/int01(p1.1)/gpio81 had2/osdr6/int00(p1.0)/gpio80 had1/osdr5/itxd0(p3.1)/gpio77 had0/osdr4/rxd0(p3.0)/gpio76 hcs/osdclk/t1(p3.5)/gpio75 spi_cs/(b:mcu_en) spi_sio3/gpio74 spi_sio2/gpio73 spi_sio1 spi_sio0 spi_clk vdd33 vss33 xtalo xtali ir/osdb3/gpio72 656_clk/osdg3/p3.2/gpio71 dtvd23/656_d7/osdr3/gpio70 dtvd22/656_d6/osdb2/gpio67 dtvd21/656_d5/osdg2/gpio66 dtvd20/656_d4/osd r2 /gpio65 dtvd19/656_d3/osdap/gpio64 dtvd18/656_d2/osdfb/gpio63 dtvd17/656_d1/osdhs/gpio62 dtvd16/656_d0/osdvs/gpio61 dtvvs/gpio60 dtvhs/gpio57 dtvde/gpio56 dtvclk dtvd15/dtvb7/gpio55 dtvd14/dtvb6/gpio54 dtvd13/dtvb5/gpio53 dtvd12/dtvb4/gpio52 vdd33 tw882 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 rin1 rin0 agndrgb reft vcom refb gin1 gin0 bin1 bin0 vssa(r,g,b) vdda(y,c) yout yin3 yin2 yin1 yin0 agndy cin0 vssa(y,c) davdd1 davdd2 dac_r dac_g dac_b davss 2 davss 1 avdd33_tsc sen0 sen1 aux3 aux2 aux1 aux0 xpuls yplus xminus yminus avss33_tsc vdd18 vss18 fpbias/ccflp/ledc/gpio00 fppwc/gpio01 fppwm/ccfln/gpio2 pwm2/(b:said)/gpio03 trclk/gpio04 tcinv/gpio05 tclp/gpio6 fpvs/trspt/gpio07 fphs/tcspl/gpio10 fpde/troe/gpio11 fpclk/tcclk/gpio12 fpr0/trudl/gpio13 fpr1/tclrl/gpio14 vss33 vdd33 fpr2/gpio15 fpr3/gpio16 fpr4/gpio17 fpr5/gpio20 fpr6/gpio21 fpr7/gpio22 fpg0/trspb/gpio23 fpg1/tcspr/gpio24 fpg2/gpio25 fpg3/gpio26 fpg4/gpio27 fpg5/gpio30 lvds vss33 lvd s vdd33 fpg6/lvds data p3 fpg7/lvds_dat n3 fpb0/tcpoln/lvds ck p fpb1/tcpolp/lvds ck n lvds vss 33 lvds vdd 33 fpb2 / lvds dat p2 fpb3 / lvds dat n2 fpb4 / lvds dat p1 fpb5 / lvds dat n1 fpb6 / lvds dat p0 fpb7 / lvds dat n0 ddr vdd18 ddr vss18 ddr_vref (1.25v) ddr adr3 ddr adr2 ddr adr1 ddr adr0 ddr adr10 ddr vssp ddr_ba1 ddr_ba0 ddr ras ddr cas ddr we ddr vdd p ddr ldm ddr data7 ddr data6 ddr data5 ddr data4 ddr vssp ddr data3 ddr data2 ddr data1 ddr data0 ddr dqs0 TW8823 ? tft flat panel controller techwell, inc. 52 rev a 11/20/2009 pin description this section provides a detailed description of eac h pin for the TW8823. the pins are arranged in func tional groups according to their associated interface. the active state of the signal is determined by the trailing symbol at the end of the signal name. a " #" symbol indicates that the signal is active or asserted at a low volt age level. when "#" is not present after the signal name, the signal is active at the high voltage level. the pin description also includes the buffer direct ion and type used for that pin. pin# i/o pin name description internal connection recommended connection of unused pin status at hw reset analog i/f signals and power 1 ai rin1 analog red input 1 connect to vssa 2 ai rin0 analog red input 0 3 ai agndrgb analog rgb input reference node 4 ai reft rgb a/d voltage reference top. connect a 0.1uf between vssa and this pin. 5 a vcom analog output for mid scale voltage 6 ai refb rgb a/d voltage reference bottom. connect a 0.1uf between vssa and this pin. 7 ai gin1 analog green input 1 8 ai gin0 analog green input 0 9 ai bin1 analog blue input 1 10 ai bin0 analog blue input 0 x 13 ao yout y output (y out or y+c out) open/uncon nected x 14 ai yin3 analog composite or luma input 3 conne ct to vssa 15 ai yin2 analog composite or luma input 2 16 ai yin1 analog composite or luma input 1 17 ai yin0 analog composite or luma input 0 18 ai agndy analog yc input reference node 19 ai cin0 analog component c input 0 213 ai sog sync on green input x 216 p vdda(rgb) analog a/d power +1.8v 11 p vssa(rgb) analog ground for r, g, b channels. connect a 0.1uf between vssa and this pin. 12 p vdda(yc) analog video a/d power +1.8v 20 p vssa(yc) analog video a/d ground 209 p ssvss ss-pll(internal analog) ground 210 p ssvdd ss-pll(internal analog) power +1.8v 211 p llvss ll- pll(internal analog) ground 212 p llvdd ll- pll (internal analog) power +1.8v 214 p alvdd low voltage analog power +1.8v - pwr TW8823 ? tft flat panel controller techwell, inc. 53 rev a 11/20/2009 215 p alvss analog ground for low voltage analog power (alvdd) dac i/f signals 21 p davdd1 dac analog power +5.0v 22 p davdd2 dac analog power +3.3v - pwr 23 ao dac_r dac analog red data output 24 ao dac_g dac analog green data output 25 ao dac_b dac analog blue data output open/unconnected x 26 p davss2 dac analog ground 27 p davss1 dac analog ground for 5v power - pwr 29 ai sen0 analog sensing 0 input / ccfl or led current sensing 30 ai sen1 analog sensing 1 input / ccfl or led voltage sensing 31 ai aux3 auxiliary channel 3 32 ai aux2 auxiliary channel 2 33 ai aux1 auxiliary channel 1 34 ai aux0 auxiliary channel 0 35 ai xplus positive x input 36 ai yplus positive y input 37 ai xminus negative x input 38 ai yminus negative y input 28 p avdd33_tsc analog power +3.3v 39 p avss33_tsc analog ground - pwr ddr 86 o ddr_adr3 ddr address 87 o ddr_adr2 ddr address 88 o ddr_adr1 ddr address 89 o ddr_adr0 ddr address 90 o ddr_adr10 ddr address 138 o ddr_adr4 ddr address 137 o ddr_adr5 ddr address 136 o ddr_adr6 ddr address 135 o ddr_adr7 ddr address 134 o ddr_adr8 ddr address 133 o ddr_adr9 ddr address 132 o ddr_adr11 ddr address 131 o ddr_adr12 ddr address 92 o ddr_ba1 ddr bank 1 93 o ddr_ba0 ddr bank 0 94 o ddr_ras ddr ras signal 95 o ddr_cas ddr cas signal 96 o ddr_we ddr we signal 98 o ddr_ldm ddr data mask 99 o ddr_data7 ddr data bus 100 o ddr_data6 ddr data bus 101 o ddr_data5 ddr data bus 102 o ddr_data4 ddr data bus TW8823 ? tft flat panel controller techwell, inc. 54 rev a 11/20/2009 104 o ddr_data3 ddr data bus 105 o ddr_data2 ddr data bus 106 o ddr_data1 ddr data bus 107 o ddr_data0 ddr data bus 128 o ddr_data8 ddr data bus 127 o ddr_data9 ddr data bus 126 o ddr_data10 ddr data bus 125 o ddr_data11 ddr data bus 123 o ddr_data12 ddr data bus 122 o ddr_data13 ddr data bus 121 o ddr_data14 ddr data bus 120 o ddr_data15 ddr data bus 108 ddr_dqs0 ddr dqs 0 110 ddr_cke ddr clock enable signal 111 o ddr_clk ddr positive clock output signal 112 o ddr_clkn ddr negative clock output signal 119 ddr_dqs1 ddr dqs 1 129 o ddr_udm ddr data mask 83, 140 p ddr_vdd18 ddr core power +1.8v 84, 141 p ddr_vss18 ddr core ground 85, 116 p ddr_vref (1.25v) ddr 1.25v reference voltage 113, 117 p ddr_vssref ddr ground for vref(1.25v) shielding 97, 109, 118, 130 p ddr_vddp ddr io power +2.5v 91, 103, 124, 139 p ddr_vssp ddr io ground 114 p dll_vdd18 dll power +1.8v 115 p dll_vss18 dll ground - pwr lcd panel i/f, tcon i/f and lvds signals o fpbias power on/off control for panel backlight bias o ccflp ccfldriver polarity (positive) o ledc mcu led 42 i/o gpio00 gpio 00 pull down o fppwc power on/off control for flat panel display 43 i/o gpio01 gpio 01 pull down o fppwm pwm control for panel backlight o ccfln ccfl driver polarity (negative) 44 i/o gpio02 gpio 02 pull down o pwm2 pwm control2 0 o (b:said) b:said 45 i/o gpio03 gpio 03 --- o trclk tcon - row driver shift clock 46 i/o gpio04 gpio 04 --- TW8823 ? tft flat panel controller techwell, inc. 55 rev a 11/20/2009 o tcinv tcon - column driver inversion 47 i/o gpio05 gpio 05 --- o tclp tcon - column driver load pulse 48 i/o gpio06 gpio 06 --- o fpvs flat panel vsync o trspt tcon - row driver starting pulse (top start) 49 i/o gpio07 gpio 07 --- o fphs flat panel hsync o tcspl tcon - column driver start pulse (left to right scan) 50 i/o gpio10 gpio 10 --- o fpde flat panel data enable o troe tcon - row driver output enable 51 i/o gpio11 gpio 11 --- o fpclk flat panel clock output o tcclk column driver clock 52 i/o gpio12 gpio 12 --- o fpr0 red flat panel output bit o trudl tcon-up down selection (up : high, down : low) 53 i/o gpio13 gpio 13 --- o fpr1 red flat panel output bit o tclrl tcon -left right selection (left : high, right : low) 54 i/o gpio14 gpio 14 --- o fpr2 red flat panel output bit 57 i/o gpio15 gpio 15 --- o fpr3 red flat panel output bit 58 i/o gpio16 gpio 16 --- o fpr4 red flat panel output bit 59 i/o gpio17 gpio 17 --- o fpr5 red flat panel output bit 60 i/o gpio20 gpio 20 --- o fpr6 red flat panel output bit 61 i/o gpio21 gpio 21 --- o fpr7 red flat panel output bit 62 i/o gpio22 gpio 22 --- o fpg0 green flat panel output bit o trspb tcon - row driver starting pulse (bottom start) 63 i/o gpio23 gpio 23 --- o fpg1 green flat panel output bit o tcspr tcon - column driver start pulse (right to left scan) 64 i/o gpio24 gpio 24 --- o fpg2 green flat panel outputs bit 65 i/o gpio25 gpio 25 --- o fpg3 green flat panel output bit 66 i/o gpio26 gpio 26 --- 67 o fpg4 green flat panel output bit --- TW8823 ? tft flat panel controller techwell, inc. 56 rev a 11/20/2009 i/o gpio27 gpio 27 o fpg5 green flat panel output bit 68 i/o gpio30 gpio 30 --- o fpg6 green flat panel output bit 71 o lvds_dat_p3 positive differential lvds 3 rd data output --- o fpg7 green flat panel output bit 72 o lvds_dat_n3 negative differential lvds 3rd data o utput --- o fpb0 blue flat panel output bit o tcpoln tcon ? column driver polarity (negative) 73 o lvds_ck_p positive differential lvds clock output --- o fpb1 blue flat panel output bit o tcpolp tcon ? column driver polarity (positive) 74 o lvds_ck_n negative differential lvds clock output --- o fpb2 blue flat panel output bit 77 o lvds_dat_p2 positive differential lvds 2nd data o utput --- o fpb3 blue flat panel output bit 78 o lvds_dat_n2 negative differential lvds 2nd data o utput --- o fpb4 blue flat panel output bit 79 o lvds_dat_p1 positive differential lvds 1st data o utput --- o fpb5 blue flat panel output bit 80 o lvds_dat_n1 negative differential lvds 1st data o utput --- o fpb6 blue flat panel output bit 81 o lvds_dat_p0 positive differential lvds 0th data o utput --- o fpb7 blue flat panel output bit 82 o lvds_dat_n0 negative differential lvds 0th data o utput --- host, external osd, dtv i/f signals i dtvr2 dtv input i/o to(p3.4) mcu port 3.4 148 i/o gpio34 gpio 34 pull down i dtv0 dtv input i dtvr3 dtv input 149 i/o gpio35 gpio 35 pull down i dtvd1 dtv input i dtvr4 dtv input 150 i/o gpio36 gpio 36 pull down i dtvd2 dtv input i dtvr5 dtv input 151 i/o gpio37 gpio 37 pull down i dtvd3 dtv input i dtvr6 dtv input 152 i/o gpio40 gpio 40 pull down i dtvd4 dtv input i dtvr7 dtv input 153 i/o gpio41 gpio 41 pull down i dtvd5 dtv input i dtvg2 dtv input 154 i/o gpio42 gpio 42 pull down TW8823 ? tft flat panel controller techwell, inc. 57 rev a 11/20/2009 i dtvd6 dtv input i dtvg3 dtv input 155 i/o gpio43 gpio 43 pull down i dtvd7 dtv input i dtvg4 dtv input 156 i/o gpio44 gpio 44 pull down i dtvd8 dtv input i dtvg5 dtv input 157 i/o gpio45 gpio 45 pull down i dtvd9 dtv input i dtvg6 dtv input 158 i/o gpio46 gpio 46 pull down i dtvd10 dtv input i dtvg7 dtv input 159 i/o gpio47 gpio 47 pull down i dtvb2 dtv input i/o p3.3 mcu port 3.3 160 i/o gpio50 gpio 50 pull down i dtvd11 dtv input i dtvb3 dtv input 161 i/o gpio51 gpio 51 pull down i dtvd12 dtv input i dtvb4 dtv input 164 i/o gpio52 gpio 52 pull down i dtvd13 dtv input i dtvb5 dtv input 165 i/o gpio53 gpio 53 pull down i dtvd14 dtv input i dtvb6 dtv input 166 i/o gpio54 gpio 54 pull down i dtvd15 dtv input i dtvb7 dtv input 167 i/o gpio55 gpio 55 pull down 168 i dtvclk clock input for dtv interface --- i dtvde data valid for dtv interface or raw hsync for dtv interface 169 i/o gpio56 gpio 56 pull down i dtvhs horizontal sync for dtv interface 170 i/o gpio57 gpio 57 pull down i dtvvs data valid for dtv interface or raw hsync for dtv interface 171 i/o gpio60 gpio 60 pull down i dtv16 dtv input i 656_d0 2 nd dtv input, 656 data 0 i osdvs external osd vertical sync signal 172 i/o gpio61 gpio 61 pull down 173 i dtv17 dtv input pull down TW8823 ? tft flat panel controller techwell, inc. 58 rev a 11/20/2009 i 656_d1 2 nd dtv input, 656 data 1 i osdhs external osd horizontal sync signal i/o gpio62 gpio 62 i dtv18 dtv input i 656_d2 2 nd dtv input, 656 data 2 i/o osdfb external osd 174 i/o gpio63 gpio 63 pull down i dtv19 dtv input i 656_d3 2 nd dtv input, 656 data 3 i osdap external osd alpha blending control signal 175 i/o gpio64 gpio 64 pull down i dtv20 dtv input i 656_d4 2 nd dtv input, 656 data 4 i osdr2 external osd r data input 176 i/o gpio65 gpio 65 pull down i dtv21 dtv input i 656_d5 2 nd dtv input, 656 data 5 i osdg2 external osd g data input 177 i/o gpio66 gpio 66 pull down i dtv22 dtv input i 656_d6 2 nd dtv input, 656 data 6 i osdb2 external osd b data input 178 i/o gpio67 gpio 67 pull down i dtv23 dtv input i 656_d7 2 nd dtv input, 656 data 7 i osdr3 external osd r data input 179 i/o gpio70 gpio 70 pull down i 656_clk 656 clock signal i osdg3 external osd g data input i/o p3.2 mcu port 3.2 180 i/o gpio71 gpio 71 pull down i ir ir i osdb3 external osd b data input 181 i/o gpio72 gpio 72 pull up 186 i/o spi_clk spi clock output --- 187 i/o spi_sio0 spi io 0 ---- 188 i/o spi_sio1 spi io 1 ---- i/o spi_sio2 spi io 2 189 i/o gpio73 gpio 73 pull up i/o spi_sio3 spi io 3 190 i/o gpio74 gpio 74 pull up i spi_cs spi cs 191 i b:mcu_en mcu eable --- i hcs host interface chip select signal i osdclk external osd clock input 192 i/o t1(p3.5) mcu port 3.5 pull up TW8823 ? tft flat panel controller techwell, inc. 59 rev a 11/20/2009 i/o gpio75 gpio 75 i had0 host interface address data i osdr4 external osd r data input i/o rxd0(p3.0) mcu port 3.0 (mcu rxd) 193 i/o gpio76 gpio 76 pull up i had1 host interface address data i osdr5 external osd r data input i txd0(p3.1) mcu port 3.1 (mcu txd) 194 i/o gpio77 gpio 77 pull up i had2 host interface address data i osdr6 external osd r data input i int00(p1.0) mcu port 1.0 195 i/o gpio80 gpio 80 pull up i had3 host interface address data i osdr7 external osd r data input i/o int01(p1.1) mcu port 1.1 196 i/o gpio81 gpio 81 pull up i had4 host interface address data i osdg4 external osd g data input i/o int02(p1.2) mcu port 1.2 197 i/o gpio82 gpio 82 pull up i had5 host interface address data i osdg5 external osd g data input i/o int03(p1.3) mcu port 1.3 198 i/o gpio83 gpio 83 pull up i had6 host interface address data i osdg6 external osd g data input i/o int04(p1.4) mcu port 1.4 199 i/o gpio84 gpio 84 pull up i had7 host interface address data i osdg7 external osd g data input i/o int05(p1.5) mcu port 1.5 200 i/o gpio85 gpio 85 pull up i hrdl host interface read indicate signal i osdb4 external osd b data input i/o int06(p1.6) mcu port 1.6 201 i/o gpio86 gpio 86 pull up i hwrl host interface write indicate signal i osdb5 external osd b data input i/o int07(p1.7) mcu port 1.7 202 i/o gpio87 gpio 87 pull up i hale host interface address latch enable signal i osdb6 external osd b data input i/o rxd1(p3.6) mcu port 3.6, rxd1 203 i/o gpio90 gpio 90 pull up 204 i hwait host interface wait signal pull up TW8823 ? tft flat panel controller techwell, inc. 60 rev a 11/20/2009 i osdb7 external osd b data input i/o txd1(p3.7) mcu port 3.7, txd1 i/o gpio91 gpio 91 hadc_vs rgb vsync 207 i/o gpio92 gpio 92 pull up hadc_hs rgb hsync 208 i/o gpio93 gpio 93 pull up other i/f signals 182 i xtali crystal terminal (if crystal is used) or oscillator input - hi-z 183 o xtalo crystal terminal (if crystal is used) 0 i/o i2c_ssdat i2c data 147 i/o gpio33 gpio 33 pull up i i2c_ssclk i2c clock 146 i/o gpio32 gpio 32 pull up o irq-out irq output data i/o gpio31 gpio 31 145 i b:boot_sel / host boot select for mcu mode parallel host type for non mcu mode --- 142 i power_dn power down control --- hi-z 144 i test chip test mode selection. connect vss -- - hi-z 143 i reset reset pin pull up - 1 TW8823 ? tft flat panel controller techwell, inc. 61 rev a 11/20/2009 digital power 70, 76 p lvds_vdd33 lvds power +3.3v 69, 75 p lvds_vss33 lvds ground 56, 163, 185 p vdd33 digital i/o power +3.3v 55, 162, 184 p vss33 digital i/o ground 40, 205 p vdd18 digital core power +1.8v 41, 206 p vss18 digital core ground - pwr *1: pull-up resistor 38k(min), 54k(typ), 83k( max) ohm *2: pull-down resistor 35k(min), 57k(typ), 107k(max ) ohm *3: " - " need opimized treatment TW8823 ? tft flat panel controller techwell, inc. 62 rev a 11/20/2009 parametric information ac/dc electrical parameters table 5. absolute maximum ratings parameter symbol min typ max units v dda33 *(measured to v ssa33 *) 3.3v vdda33m - - 3.6 v v dda18 * (measured to v ssa18 *) 1.8v vddam - - 1.92 v v dd18 *(measured to v ss18 *) 1.8v vdd18m - - 1.98 v v ddl33 (measured to v ssl33 ) 3.3v vddl33m - - 3.6 v v dd33 (measured to v ss33 ) 3.3v vdd33m - - 3.6 v v dd25 *(measured to v ss25 *) 2.5v (ddr) vdd25m - - 2.7 v v ddref *(measured to v ssref *) 1.25v vddrefm - - 1.35v voltage on any digital signal pin (see the note below) - v ss33 ? 0.5 - 5.5 v analog input voltage (supplied by 1.8v) - v ssa18 ? 0.5 - 1.92 v analog input voltage (suppied by 3.3v) - v ssa33 - 0.5 3.6 v storage temperature t s ?65 - +150 c junction temperature t j - - +125 c reflow soldering tpeak 255 +5/-0 (10~30 seconds) c note * : v dda33 : davdd1, davdd2, avdd33_tsc v ssa33 : davss1, davss2, avss33_tsc v dda18 : vdda, dll_vdd18, ssvdd, llvdd, alvdd v ssa18 : vssa, dll_vss18, ssvss, llvss, alvss v ddl33 : lvds_vdd33 v ssl33 : lvds_vss33 v dd33 : vdd33 v ss33 vss33 v dd25 : ddr_vddp v ss25 : ddr_vssp v dd18 : vdd18, ddr_vdd18 v ss18 : vss18, ddr_vss18 v ddref : ddr_vref v ssref : ddr_vssref note: stresses above those listed may cause permanent dam age to the device. this is a stress rating only, an d functional operation at these or any other conditions above those listed in the operatio nal section of this specification is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devices on all signal pins. it must be handled as an esd-sensi tive device. voltage on any signal pin that exceeds the ranges list in table 4 can induce destructive latch-up. TW8823 ? tft flat panel controller techwell, inc. 63 rev a 11/20/2009 table 6. characteristics parameter symbol min typ max units supply power supply ? io 3.3v v dd33 3.15 3.3 3.6 v power supply io 2.5v (ddr) v dd25 2.3 2.5 2.7 v power supply ? digital core 1.8v v dd18 1.62 1.8 1.98 v reference voltage supply 1.25v v ddref 1.15 1.25 1.35 v power supply ? lvds 3.3v v ddl33 3.15 3.3 3.6 v power supply ? analog 3.3v v dda33 3.15 3.3 3.6 v power supply ? analog 1.8v v dda18 1.62 1.8 1.92 v ambient operating temperature t a -40 +85 c analog supply current 3.3v iaa33 - tbd - ma analog supply current 1.8v (cvbs) iaa18 - tbd - ma lvds supply current 3.3v* iddl33 - tbd - ma digital i/o supply current 3.3v* idd33 - tbd - ma digital i/o supply current 2.5v* idd25 - tbd - ma digital core supply current* idd18 - tbd - ma digital reference supply current idd125 - tbd - ma * note : digital i/o and core power supply current measurement is base on wvga input (40mhz clock rate ) with smpte pattern. mclk is set at 120mhz. parameter symbol min typ max units digital inputs input high voltage (ttl) v ih 2.0 - - v input low voltage (ttl) v il - - 0.8 v input high voltage (xti) v ih 2.0 - v dd33 + 0.5 v input low voltage (xti) v il - - 0.8 v input high voltage (ddr) v ih v ddref + 0.18 - v dd25 + 0.3 v input low voltage (ddr) v il -0.3 - v ddref - 0.18 v input high current (v in =v dd ) i ih - - 10 a input low current (v in =vss) i il - - ?10 a input capacitance (f=1 mhz, v in =2.4 v) c in - 5 - pf digital outputs output high voltage (i oh = ?4ma) v oh 2.4 - v dd33 v output low voltage (i ol = 4ma) v ol - 0.2 0.4 v 3-state current i oz - - 10 a output capacitance c o - 5 - pf TW8823 ? tft flat panel controller techwell, inc. 64 rev a 11/20/2009 parameter symbol min typ max units analog input analog pin input voltage vi - 1 - vpp yin0, yin1 , yin2 and yin3 input range (ac coupling required) 0.5 1.0 2.0 vpp cin0 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp rin0, rin1 , gin0, gin1, bin0, and bin1 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp sen0, sen1 dc input range 0.65 1.65 2.65 v soyin input range 0.02 0.3 1.8 v analog pin input capacitance c a - 7 - pf adcs adc resolution adcr - 9 - bits adc integral non-linearity ainl - 1 - lsb adc differential non-linearity adnl - 1 - lsb adc clock rate f adc - 27 60 mhz video bandwidth (-3db) bw - 10 - mhz parameter symbol min typ max units horizontal pll line frequency (50hz) f ln - 15.625 - khz line frequency (60hz) f ln - 15.734 - khz static deviation ? f h - - 6.2 % subcarrier pll subcarrier frequency (ntsc-m) f sc - 3579545 - hz subcarrier frequency (pal-bdghi) f sc - 4433619 - hz subcarrier frequency (pal-m) f sc - 3575612 - hz subcarrier frequency (pal-n) f sc - 3582056 - hz lock in range ? f h 450 - - hz crystal spec nominal frequency (fundamental) - 27 - mhz deviation - - 50 ppm load capacitance cl - 20 - pf series resistor rs - 80 - ohm *note : crystal deviation crossover normal operatio n temperature range TW8823 ? tft flat panel controller techwell, inc. 65 rev a 11/20/2009 filter curves anti-alias filter decimation filter 0 2 4 6 8 10 12 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10 7 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db) TW8823 ? tft flat panel controller techwell, inc. 66 rev a 11/20/2009 chroma band pass filter curves luma notch filter curve for ntsc and pal 0 1 2 3 4 5 6 7 8 9 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) pal/seam ntsc 0 1 2 3 4 5 6 7 8 x 10 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 frequency (hertz) gain (db) ntsc pal TW8823 ? tft flat panel controller techwell, inc. 67 rev a 11/20/2009 chrominance low-pass filter curve low med high 0 1 2 3 4 5 6 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db) cbw=0 cbw=3 cbw=1 cbw=2 TW8823 ? tft flat panel controller techwell, inc. 68 rev a 11/20/2009 mechanical data 216 lqfp TW8823 ? tft flat panel controller techwell, inc. 69 rev a 11/20/2009 notes: 1. dimensions d1 and e1 do not include mold protrus ion. 2. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lea d width to exceed the maximum b dimension by more tha n 0.08mm. dambar can not be located on the lower radius or th e foot. minimum space between protrusion and a adjacent lead is 0.07mm. millimeter inch symbol min nom max min nom max a --- --- 1.60 --- --- 0.063 a1 0.05 --- 0.15 0.002 --- 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 26.00 bsc. 1.024 bsc. d1 24.00 bsc. 0.945 bsc. e 26.00 bsc. 1.024 bsc. e1 24.00 bsc. 0.945 bsc. r2 0.08 --- 0.20 0.003 --- 0.008 r1 0.08 --- --- 0.003 --- --- ? 0 3.5 7 0 3.5 7 ? 1 0 --- --- 0 --- --- ? 2 11 12 13 11 12 13 ? 3 11 12 13 11 12 13 c 0.09 --- 0.20 0.004 --- 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 --- --- 0.008 --- --- b 0.13 0.16 0.23 0.005 0.006 0.009 e 0.40 bsc. 0.016 bsc. d2 21.20 0.835 e2 21.20 0.835 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.07 0.003 control dimensions are in millmeters. TW8823 ? tft flat panel controller techwell, inc. 70 rev a 11/20/2009 TW8823 register summary the registers are organized in functional groups in this register summary. a register containing diff erent functional bits may appear more than once in different functio nal groups. if a particular bit of a register is not related to that functional group, it is printed in smaller fo nt than those related. for example, bit 7 of index 006 is classified as ?gener al? and is printed in normal size; the other bits i n this register are printed in smaller size for their functionality is not classified as ?general?. general (common for any page) index (hex) 7 6 5 4 3 2 1 0 reset value 0x??ff page[7:0] 00h total total total total pages : pages : pages : pages : 16 ( 16 ( 16 ( 16 ( 0~f) 0~f) 0~f) 0~f) page # register group page # register group page # register group page # register group 0 common 4 scaler b measure d ccfl/tsc/ lvds/ remo/lopor /sspll/dac 1 decoder 5 ie c ddr/dll/ aux_ddr 2 inpif_rgb 6 pip f mcu 3 inpif_dtv1/ inpif_dtv2 7 osd 8 eosd 9 waver,tga a tcon TW8823 ? tft flat panel controller techwell, inc. 71 rev a 11/20/2009 global register index (hex) 7 6 5 4 3 2 1 0 reset value 000 id rev 28h 040 gpio_en 0[7:0] 00h 041 gpio_en 1[7:0] 00h 042 gpio_en 2[7:0] 00h 043 gpio_en 3[7:0] 00h 044 gpio_en 4[7:0] 00h 045 gpio_en 5[7:0] 00h 046 gpio_en 6[7:0] 00h 047 gpio_en 7[7:0] 00h 048 gpio_en 8[7:0] 00h 049 gpio_en 9[7:0] 00h 050 gpio_oe 0[7:0] 00h 051 gpio_oe 1[7:0] 00h 052 gpio_oe 2[7:0] 00h 053 gpio_oe 3[7:0] 00h 054 gpio_oe 4[7:0] 00h 055 gpio_oe 5[7:0] 00h 056 gpio_oe 6[7:0] 00h 057 gpio_oe 7[7:0] 00h 058 gpio_oe 8[7:0] 00h 059 gpio_oe 9[7:0] 00h 060 gpio_id 0[7:0] 00h 061 gpio_id 1[7:0] 00h 062 gpio_id 2[7:0] 00h 063 gpio_id 3[7:0] 00h 064 gpio_id 4[7:0] 00h 065 gpio_id 5[7:0] 00h 066 gpio_id 6[7:0] 00h 067 gpio_id 7[7:0] 00h 068 gpio_id 8[7:0] 00h 069 gpio_id 9[7:0] 00h 070 gpio_od 0[7:0] 00h 071 gpio_od 1[7:0] 00h 072 gpio_od 2[7:0] 00h 073 gpio_od 3[7:0] 00h 074 gpio_od 4[7:0] 00h 075 gpio_od 5[7:0] 00h 076 gpio_od 6[7:0] 00h 077 gpio_od 7[7:0] 00h 078 gpio_od 8[7:0] 00h 079 gpio_od 9[7:0] 00h 080 - - - - testgpo testgposel[2:0] 00h TW8823 ? tft flat panel controller techwell, inc. 72 rev a 11/20/2009 index (hex) 7 6 5 4 3 2 1 0 reset value 090 pullud_en_0[7:0] ffh 091 pullud_en_1[7:0] ffh 092 pullud_en_2[7:0] ffh 093 pullud_en_3[7:0] f3h 094 pullud_en_4[7:0] ffh 095 pullud_en_5[7:0] ffh 096 pullud_en_6[7:0] ffh 097 pullud_en_7[7:0] ffh 098 pullud_en_8[7:0] ffh 099 pullud_en_9[7:0] f3h index (hex) 7 6 5 4 3 2 1 0 reset value 0a0 pwronrst n i2scs mcuen host bootse l hcsl pwrdn test 00h 0a1 dualdtvmode[1:0] ( 211[7:6]) - - - - - sacnt ( 0e8[0]) 00h 0aa selpadcl kp selpadclkm - - - pckcap[1:0] 00h 0ab clock_pol ( 213[7:0]) 00h 0ac merge_cn ( 20e[7]) - - - - - ckpol_dec mainpathck pol ( 210[0]) 00h 0ad clkpdall ( 0e8[7]) clkpwrdn[6:0] 00h TW8823 ? tft flat panel controller techwell, inc. 73 rev a 11/20/2009 status & interrupt index (hex) 7 6 5 4 3 2 1 0 reset value 0b0 lb_ovf lb_unf v_los_c h_los_c vdlos_c v_loss h_loss syncs 00h 0b1 m_rdy pws_c v_prd_c h_prd_c lbounf vdc_c vh_los_c syncs_c 00h 0b2 irq_b_b17 irq_b_b16 irq_b_b15 irq_b_b14 irq_b_b13 irq_b_b12 irq_b_b11 irq_b_b10 ffh 0b3 - - irq_b_vd irq_b_cc irq_b_50 07h 0b4 - - p_vlos_ c p_vlos_ c - p_vloss p_hloss p_syncs 00h 0b5 - - p_vprd_ c p_hprd_ c - - p_vhlos c p_syncs c 00h 0b6 - - m_vlos_ c m_vlos_ c - m_vloss m_hloss m_syncs 00h 0b7 - - m_vprd_ c m_hprd_ c - - m_vhlos c m_syncs 00h 0b8 - irq_1b5_ 5 irq_1b5_ 4 - - irq_1b5_ 1 irq_1b5_ 0 00h 0b9 irq_1b7_ 5 irq_1b7_ 4 irq_1b7_ 1 irq_1b7_ 0 00h 0ba irq_oe irq_al irq_sts - - - - - 00h internal test index (hex) 7 6 5 4 3 2 1 0 reset value 0c6 sel_c grayd data_0 datablu tlmode - - 00h 0c7 bwymin - 0c8 bwymax - 0c9 bwfmin - 0ca bwfmax - 0cb bwbtilt - 0cc bwwtilt - 0cd - 0ce test_mode 00h 0cf - - - - - - - 00h 0e0 swrst llbff ? 00h TW8823 ? tft flat panel controller techwell, inc. 74 rev a 11/20/2009 decoder index (hex) 7 6 5 4 3 2 1 0 reset value 0101 vdloss hlock slock field vlock - mono det50 - 0102 ysel2 fc27 ifsel ysel csel - 40h 0103 - - 0104 - ckhy - 00h 0105 - - 0106 decrst pdmix fbp agc_en clkpdn y_pdn c_pdn v_pdn 03h 0107 vdelay_hi vactive_hi hdelay_hi hactive_hi 02h 0108 vdelay_lo 15h 0109 vactive_lo - 010a hdelay_lo - 010b hactive_lo d0h 010c pbw dem palsw set7 comb hcomp ycomb pdly 8ch 010d - - - - 15h 010e - - - - 010f - - 0110 brightness 00h 0111 contrast 60h 0112 scurve vsf cti sharpness 51h 0113 sat_u 80h 0114 sat_v 80h 0115 hue 00h 0116 - - - 0117 shcor - vshp 30h 0118 ctcor ccor vcor cif 44h 0119 - - 011a - eds_en cc_en parity ff_ovf ff_emp cc_eds lo_hi 011b cc_data 011c dtstus stdnow atreg standard 00h 011d start pal60 palcn palm ntsc4 secam palb ntsc 00h 011e - cvstd cvfmt 08h 011f - vref iref save 00h TW8823 ? tft flat panel controller techwell, inc. 75 rev a 11/20/2009 decoder index (hex) 7 6 5 4 3 2 1 0 reset value 0120 clpend clpst 50h 0121 nmgain wpgain agcgain 42h 0122 agcgain f0h 0123 peakwt d8h 0124 clmpld clmpl bch 0125 synctd synct b8h 0126 misscnt hswin 44h 0127 pclamp 2ah 0128 vlcki vlcko vmode detv afld vint 00h 0129 bsht vsht 15h 012a ckillmax ckillmin a0h 012b htl vtl 44h 012c cklm ydly hflt 30h 012d hplc evcnt palc sdet tbc_en bypass syout hadv 14h 012e hpm acct spm cbvv a5h 012f nkill pkill skill cbal fcs lcs ccs bst e0h 0130 sid_fail pid_fail fsc_fail slock_f ail csbad mvcsn cstripe ctype - 0131 vcr wkair wkair1 vstd nintl wssdet edsdet ccdet - 0132 hfref/gval/pherrdo/cgaino/bampo/minavg/sythrd/syamp - 0133 frm ynr clmp psp 05h 0134 index nsen/ssen/psen/wkth 1ah 0135 ctest yclen cclen vclen gtest vlpf ckly cklc 10h 0136 00h 0137 00h 0138 - sy_c 00h lcdc C 3d comb/nr control index (hex) 7 6 5 4 3 2 1 0 reset value 0160 md_th 08h 0161 - 00h 0162 3den mixmd1 mixmd2 - - test3d tm_3d 00h 0163 - 80h 0164 - 53h 0165 mstretch 4ch 0166 - 4bh 0167 testnr nren nrgain nrlevel 14h 0168 nonstd - - - - ns_lnum ns_llen ns_flen 07h 0169 nsth1 02h 016a nsth2 03h 016b nson nsoff c1h 016c - 00h 016d - 98h 016e - - - - - - - - 00h 016f - - - - - - - - 00h TW8823 ? tft flat panel controller techwell, inc. 76 rev a 11/20/2009 lcdc C iirgb (input interface rgb) index (hex) 7 6 5 4 3 2 1 0 reset value 0200 - - - - - hs_pol vs_pol sdelvs 00h 0201 vsdelay 00h 0202 - - - - - - - yuv_rgb 00h 0203 ofd_stop ofd_start 54h 0204 rvoddp ofdmthd rgb_sdfl d slvsfld - ck_dly 20h lcdc : adc/llpll index (hex) 7 6 5 4 3 2 1 0 reset value 02c0 inpselsog cs_inv cs_sel sog_sel hs_pol hs_sel outckse l 00h 02c1 vs_pol hs_pol vs_det hs_det cs_det in_src 02c2 llc_post llc_vco - llc_ipmp 00h 02c3 ll_rstvc o ll_insel ll_icpsel llc_ackn[11:8] 03h 02c4 llc_ackn[7:0] 5ah 02c5 llc_pha 00h 02c6 llc_acpl llc_apg - llc_apz 20h 02c7 ll_test ll_bufe ll_vinen ll5pf llc_acki[11:8] 04h 02c8 llc_acki[7:0] 00h 02c9 pre_coast 06h 02ca post_coast 06h 02cb pusog pupll - sog_th 30h 02cc llclk_dly pinvssel hsy_sel vsy_polc hsy_polc 00h 02ce pinhssel pdr pdg pdb dtv clpen inrefi inrefi 00h 02cf inp_sel_adc save 24h 02d0 - gainy[8] gainc[8] gainv[8] 00h 02d1 gainy f0h 02d2 gainc f0h 02d3 gainv f0h 02d4 rgb_mode - cl_edge ckly cklc y_cl_en c_cl_en v_cl_en 00h 02d5 cl_start 00h 02d6 cl_end 12h 02d7 cl_loc 70h 02d8 - llc_dbg_sel cl_test adc_test cl_y_test cl_uv_test 00h 02d9 cl_g_val 10h 02da cl_b_val 80h 02db cl_r_val 80h 02dc edge_sel _ll - hswid[5:0] 20h 02dd offsetr 00h 02de offsetg 00h 02df offsetb 00h TW8823 ? tft flat panel controller techwell, inc. 77 rev a 11/20/2009 lcdc C iidtv 1 (input interface dtv 1) index (hex) 7 6 5 4 3 2 1 0 reset value 0300 ofdm rvoddp slvsfld deonly de_pol hs_pol vs_pol - 00h 0301 - - ext_ha selde - dtvck_delay 20h 0302 - - vsdl_65 6 uva656 cr601 input_data_bus_routing 04h 0303 - - - - inp_form 28h 0304 ofd_det_end ofd_det_st 54h 0305 sel_hmx - - - - - - - 00h 0306 vsdelay[7:0] 00h 0307 seqrgb_ltg[1:0] seqrgb_order[1:0] seqrgb_sel8bit[1: 0] seqrgb_pol seqrgb 00h 0310 - 00h 0311 - 00h 0312 - - - 00h 0313 tpg_en tpg_swap[2:0] tpg_pat[3:0] 00h lcdc C iidtv 2 (input interface dtv 2) index (hex) 7 6 5 4 3 2 1 0 reset value 0320 ofdm rvoddp slvsfld deonly de_pol hs_pol vs_pol - 00h 0321 - - ext_ha selde - dtvck_delay 20h 0322 - - vsdl_656 uva656 cr601 input_data_bus_routing 04h 0323 - - - - inp_form 28h 0324 ofd_det_end ofd_det_st 54h 0325 sel_hmx - - - - - - - 00h 0326 vsdelay[7:0] 00h 0327 seqrgb_ltg[1:0] seqrgb_order[1:0] seqrgb_sel8bit[1: 0] seqrgb_ pol seqrgb 00h 0330 - 00h 0331 - 00h 0332 - - - 00h 0333 tpg_en tpg_swap[2:0] tpg_pat[3:0] 00h TW8823 ? tft flat panel controller techwell, inc. 78 rev a 11/20/2009 lcdc C main path input cropping index (hex) 7 6 5 4 3 2 1 0 reset value 0400 sw_rst_ scaler rvoddp9 9(decfldin v) lb_ce - - ip_sel 00h 0410 - - - - - 00h 0411 ip_ha_st [10:0] 00h 0412 - - - - 02h 0413 ip_ha_len [11:0] d0h 0414 - - - - - - 00h 0415 ip_va_st_odd [9:0] 13h 0416 evn_off set_neg ip_va_st_evn_offset [6:0] 01h 0417 - - - - 03h 0418 ip_va_len [10:0] 00h lcdc C scaling index (hex) 7 6 5 4 3 2 1 0 reset value 0430 - - - - - - - 00h 0431 x_scale_up [16:0] b4h 0432 00h 0433 - - - - - - - 00h 0434 x_scale_down [8:0] 80h 0435 - - - - - - 00h 0436 y_scale_up/down [17:0] 50h 0437 00h 0438 x_offset 00h 0439 y_offset_odd 00h 043a y_offset_even 80h 043b - lndb pxdb zoombp - - - 00h 043c pano_en a - - - - - panorama_width [9:8] 00h 043d panorama_width [7:0] 00h 043e x_scale_up_pan (at_the_side_for_panorama) 00h 043f dnsfil_m an - - - - - dnsfil_mode 00h TW8823 ? tft flat panel controller techwell, inc. 79 rev a 11/20/2009 lcdc C panel display control index (hex) 7 6 5 4 3 2 1 0 reset value 0470 rgb2bsf t_up dual_se lh fpdata_ zero - - - data_0 data_bl u 00h 0471 swap_fp rgb - demode op6b trifp - 00h 0472 - - - - 05h 0473 fphs_period [11:0] 3ah 0474 fphs_pw [7:0] 10h 0475 fphs_back_porch [7:0] 1bh 0476 - - - - - 04h 0477 fp_h_active [10:0] 00h 0478 - - - - - 03h 0479 fpvs_period [10:0] 26h 047a fpvs_pw [7:0] 06h 047b fpvs_back_porch [7:0] 1fh 047c - - - - - 03h 047d fp_v_active [10:0] 00h 0480 - - - - - - 00h 0481 thnd [9:0] 00h 0482 thnd2_e n - - - - - 00h 0483 thnd2 [9:0] 00h 0484 - - - blktb [4:0] 00h 0485 blktb2_e n - - blktb2 [4:0] 00h 0486 int_de_n o_dly - - - fpen_dly[3:0] 00h 0487 - - - - fphs_output_delay [3:0] 00h 0488 - - - - delay fpvs [3:0] 08h 0489 utvb uthb dist_had h ena_had j - - autoc usereg 00h 048a - - early_s t - afrun frerun - tcon_de _con 00h 048b line_vsc l frm_alin fld_alin alow_qe r thrsh_vchg [3:0] 04h 048c linegonum [7:0] 24h 048d disp_sngfld rvf_ac oldtime - - evndly 00h 048e - 00h 048f - 00h 0490 - - - 00h 0491 ini_cnt_odd [12:0] c0h 0492 - - - 00h 0493 ini_cnt_evn [12:0] c0h 0494 tgtpos [7:0] c0h 0495 - 00h 04c0 counter_read_byte_3 00h 04c1 counter_read_byte_2 00h 04c2 counter_read_byte_1 00h 04c3 counter_read_byte_0 00h 04c4 pccinia_index - - frc_2f frc_1f pccinia_sub_indx 00h TW8823 ? tft flat panel controller techwell, inc. 80 rev a 11/20/2009 04c5 pcctid 00h 04c6 counter_read_index - 00h TW8823 ? tft flat panel controller techwell, inc. 81 rev a 11/20/2009 lcdc C image adjustment index (hex) 7 6 5 4 3 2 1 0 reset value 0500 - - hue 20h 0501 contrast_r 80h 0502 contrast_g 80h 0503 contrast_b 80h 0504 contrast_y 80h 0505 contrast_cb 80h 0506 contrast_cr 80h 0507 brightness_r 80h 0508 brightness_g 80h 0509 brightness_b 80h 050a brightness_y 80h 050b h_sharp_cor h_sharpness 3fh 050c h_sharp_f req - dynr - hflt 00h 0510 - hue2 20h 0511 contrast_r2 80h 0512 contrast_g2 80h 0513 contrast_b2 80h 0514 contrast_y2 80h 0515 contrast_cb2 80h 0516 contrast_cr2 80h 0517 brightness_r2 80h 0518 brightness_g2 80h 0519 brightness_b2 80h 051a brightness_y2 80h 051b h_sharp_cor2 h_sharpness2 3fh 051c h_sharp_f req2 - dynr2 - hflt2 00h 0520 - - hue3 20h 0521 contrast_r3 80h 0522 contrast_g3 80h 0523 contrast_b3 80h 0524 contrast_y3 80h 0525 contrast_cb3 80h 0526 contrast_cr3 80h 0527 brightness_r3 80h 0528 brightness_g3 80h 0529 brightness_b3 80h 052a brightness_y3 80h 052b h_sharp_cor3 h_sharpness3 3fh 052c h_sharp_ freq3 - dynr3 - hflt3 00h 0530 t_bw - pedlvl whtlvl - - bpbw - 1ch 0531 bw_line_st_lo 08h 0532 bw_line_end_lo f6h 0533 - bw_line_end_hi bw_line_st_hi 08h 0534 bw_h_delay 10h TW8823 ? tft flat panel controller techwell, inc. 82 rev a 11/20/2009 lcdc C image adjustment index (hex) 7 6 5 4 3 2 1 0 reset value 0535 - bw_h_filter_gain 0bh 0536 bw_black_tilt 67h 0537 bw_white_tilt 94h 0538 bw_black_gain 2ah 0539 bw_white_gain d0h 053a - bw_gain 02h 053b - 10h 0550 ce_center0 3dh 0551 ce_center1 c3h 0552 ce_center2 fch 0553 ce_en ce_spread0 ce_gain0 00h 0554 - ce_spread1 ce_gain1 00h 0555 - ce_spread2 ce_gain2 00h 0556 - 0558 - 0570 tpg_en swap[2:0] pttn_sel[3:0] 00h TW8823 ? tft flat panel controller techwell, inc. 83 rev a 11/20/2009 lcdc C pip1 control index (hex) 7 6 5 4 3 2 1 0 reset value 8200 - pipgw_xst[9:8] 00h 8201 pipgw_xst[7:0] 00h 8202 - pipgw_width[10:8] 02h 8203 pipgw_width[7:0] d0h 8204 - pipgw_y st[8] 00h 8205 pipgw_yst[7:0] 02h 8206 - pipgw_height[10:8] 00h 8207 pipgw_height[7:0] e0h 8208 ppfil_ma n ck_inv ppfil_sel pip_efdoff pip_ofdoff 00h 8209 - pipdnsxfac[11:8] 01h 820a pipdnsxfac[7:0] 00h 820b - pipdnsyfac[11:8] 01h 820c pipdnsyfac[7:0] 00h 820d vsoff_en dnsvs_offset 00h 820e pip_wr_base[23:16] 00h 820f pip_wr_base[15:8] 00h 8210 pip_wr_base[7:0] 00h 8211 - pip_wr_width[10:8] 02h 8212 pip_wr_width[7:0] d0h 8213 - pip_wr_height[9:8] 00h 8214 pip_wr_height[7:0] e0h 8215 wren wcph mute_c - rcph 40h 8216 rden frm_md pipen sngl_fd rdfdpol pxdb lndb mute_en 00h 8217 - pupsxfac[11:8] 08h 8218 pupsxfac[7:0] 00h 8219 - pupsyfac[11:8] 08h 821a pupsyfac[7:0] 00h 821b upsvs_offset 00h 821c - pipwbasex[11:8] 00h 821d pipwbasex[7:0] 00h 821e - pipwbasey[10:8] 00h 821f pipwbasey[7:0] 00h 8220 pipwyoff pipwxoff 3ah 8221 - pipwwidth[11:8] 02h 8222 pipwwidth[7:0] d0h 8223 - pipwheight[10:8] 00h 8224 pipwheight[7:0] e0h 8225 pip_h_pos_adj f7h 8226 pip_v_pos_adj fch 8227 - 00h TW8823 ? tft flat panel controller techwell, inc. 84 rev a 11/20/2009 lcdc C pip2 control index (hex) 7 6 5 4 3 2 1 0 reset value 8230 - pip2gw_xst[9:8] 00h 8231 pip2gw_xst[7:0] 00h 8232 - pip2gw_width[10:8] 02h 8233 pip2gw_width[7:0] d0h 8234 - pip2gw_ yst[8] 00h 8235 pip2gw_yst[7:0] 02h 8236 - pip2gw_height[10:8] 00h 8237 pipgw_height[7:0] e0h 8238 ppfil_ma n ck_inv ppfil_sel pip2_efdoff pip2_ofdoff 00h 8239 - pip2dnsxfac[11:8] 01h 823a pip2dnsxfac[7:0] 00h 823b - pip2dnsyfac[11:8] 01h 823c pip2dnsyfac[7:0] 00h 823d vsoff_en dnsvs_offset 00h 823e pip2_wr_base[23:16] 00h 823f pip2_wr_base[15:8] 00h 8240 pip2_wr_base[7:0] 00h 8241 - pip2_wr_width[10:8] 02h 8242 pip2_wr_width[7:0] d0h 8243 - pip2_wr_height[9:8] 00h 8244 pip2_wr_height[7:0] e0h 8245 wren wcph mute_c - rcph 40h 8246 rden frm_md pipen sngl_fd rdfdpol pxdb lndb mute_en 00h 8247 - p2upsxfac[11:8] 08h 8248 p2upsxfac[7:0] 00h 8249 - p2upsyfac[11:8] 08h 824a p2upsyfac[7:0] 00h 824b upsvs_offset 00h 824c - pip2wbasex[11:8] 00h 824d pip2wbasex[7:0] 00h 824e - pip2wbasey[10:8] 00h 824f pip2wbasey[7:0] 00h 8250 pip2wyoff pip2wxoff 3ah 8251 - pip2wwidth[11:8] 02h 8252 pip2wwidth[7:0] d0h 8253 - pip2wheight[10:8] 00h 8254 pip2wheight[7:0] e0h 8255 pip2_h_pos_adj f7h 8256 pip2_v_pos_adj fch 8257 - 00h TW8823 ? tft flat panel controller techwell, inc. 85 rev a 11/20/2009 lcdc C pip1/pip2 common control index (hex) 7 6 5 4 3 2 1 0 reset value 8260 pip2_mrr pip_border_h pip1_mrr pip_border_w 00h 8261 mpip_frmcolor1[7:0] 1ch 8262 mpip_frmcolor2[7:0] 00h 8263 pip_rstn - 00h lcdc C dv, pip1/pip2 common control index (hex) 7 6 5 4 3 2 1 0 reset value 8270 half_pc k dv_rev pnl_dv dv_chkr dv_lrsame pip_swa p dv_en 00h 8271 dvlden1 dvlden2 dvlden3 - pip1_insel pip2_insel c0h 8272 pmx_insel pmx1_en pmx2_en alpmx2_ en sndpip pip2w_p dn pip1w_p dn f0h lcdc C pip alpha blending control index (hex) 7 6 5 4 3 2 1 0 reset value 8280 blend_en mode565 key_rev alpha1 10h 8281 keydisp - alpha2 10h 8282 rkey 00h 8283 gkey 00h 8284 bkey 00h 8285 rrang 00h 8286 grang 00h 8287 brang 00h TW8823 ? tft flat panel controller techwell, inc. 86 rev a 11/20/2009 lcdc C osd index (hex) 7 6 5 4 3 2 1 0 reset value 0700 osg_mode msksel color_c on bpp bexpm 0701 osg_stu s fifo_stu s - - - - mcuwd op_star t 0702 data por for mcu/dma write operation 0703 - osd_hw - sp8to16 osg16form osdsrst 0704 - - - rlc_pkt e - - rlc_res et rlc_ena 0705 rlc_dcnt rlc_cntt 0706 osd test - - - - osdpdn 070b bitblt logic 070c bitblt mask (hb) 070d bitblt mask (lb) 070e block fill color (hb) 070f block fill color (lb) 0710 0711 0712 0713 0714 0715 0716 0717 0718 0719 071a 071b 071c 071d 071e 071f bit expansion table for 8 bit osd 0720 0721 0722 0723 0724 0725 0726 0727 0728 0729 072a 072b 072c 072d 072e 072f 0730 bit expansion table for 16 bit osd TW8823 ? tft flat panel controller techwell, inc. 87 rev a 11/20/2009 0731 0732 0733 0734 0735 0736 0737 0738 0739 073a 073b 073c 073d 073e 073f 0740 0741 color conversion source color # 0 0742 0743 color conversion source color # 1 0744 0745 color conversion source color # 2 0746 0747 color conversion source color # 3 0748 0749 color conversion target color # 0 074a 074b color conversion target color # 1 074c 074d color conversion target color # 2 074e 074f color conversion target color # 3 0750 0751 selective overwrite # 0 0752 0753 selective overwrite # 1 0754 0755 selective overwrite # 2 0756 0757 selective overwrite # 3 0760 0761 0762 source buffer memory starting address [23:0] 0763 source buffer memory horizontal length [7:0] 0764 - - 0765 transfer source horizontal start [10:0] 0766 - - 0767 transfer source vertical start [10:0] 0768 - 0769 transfer horizontal length [11:0] 076a - 076b transfer vertical length [11:0] 0770 destination buffer memory starting address [23:0] TW8823 ? tft flat panel controller techwell, inc. 88 rev a 11/20/2009 0771 0772 0773 destination buffer memory horizontal length [7:0] 0774 - - 0775 transfer destination horizontal start [10:0] 0776 - - 0777 transfer destination vertical start [10:0] osd index (hex) 7 6 5 4 3 2 1 0 reset value 0778 bltsel flip mirror - - fupdate osdupda te 0779 - - - - - osd gain 077a look up table select - - - - - - 077b address pointer for 8 bit osd look up table 077c look up table data port byte 3 077d look up table data port byte 2 077e look up table data port byte 1 077f look up table data port byte 0 0780 - - win0_pe rpix win0_alp ha_ena - - - win0_en a 0781 - - - - - 0782 osd window 0 horizontal start [10:0] 0783 - - - - - 0784 osd window 0 vertical start [10:0] 0785 - - - - 0786 osd window 0 horizontal length [11:0] 0787 - - - - 0788 osd window 0 vertical length [11:0] 0789 078a 078b window 0 buffer memory starting address [23:0] 078c window 0 buffer memory horizontal length [7:0] 078d window 0 buffer memory vertical length [7:0] 078e - - - - - 078f window 0 image horizontal start [10:0] 0790 - - - - - 0791 window 0 image vertical start [10:0] 0792 - window 0 global alpha value 07a0 - - win1_pe rpix win1_alp ha_ena - - - win1_en a 07a1 - - - - - 07a2 osd window 1 horizontal start [10:0] 07a3 - - - - - 07a4 osd window 1 vertical start [10:0] 07a5 - - - - 07a6 osd window 1 horizontal length [11:0] 07a7 - - - - 07a8 osd window 1 vertical length [11:0] TW8823 ? tft flat panel controller techwell, inc. 89 rev a 11/20/2009 07a9 07aa 07ab window 1 buffer memory starting address [23:0] 07ac window 1 buffer memory horizontal length [7:0] 07ad window 1 buffer memory vertical length [7:0] 07ae - - - - - 07af window 1 image horizontal start [10:0] 07b0 - - - - - 07b1 window 1 image vertical start [10:0] 07b2 - window 1 global alpha value 07c0 rev_cbr - win4_pe rpix win4_alp ha_ena osd16form win4_en a 07c1 - - - - - 07c2 osd window 4 horizontal start [10:0] 07c3 - - - - - 07c4 osd window 4 vertical start [10:0] 07c5 - - - - 07c6 osd window 4 horizontal length [11:0] 07c7 - - - - 07c8 osd window 4 vertical length [11:0] 07c9 07ca 07cb window 4 buffer memory starting address [23:0] 07cc window 4 buffer memory horizontal length [7:0] 07cd window 4 buffer memory vertical length [7:0] 07ce - - - - - 07cf window 4 image horizontal start [10:0] 07d0 - - - - - 07d1 window 4 image vertical start [10:0] 07d2 - window 4 global alpha value 07d4 07d5 color key # 0 07d6 07d7 color key # 1 07d8 07d9 color key # 2 07da 07db color key # 3 07dc - alpha value for color key # 0 07dd - alpha value for color key # 1 07de - alpha value for color key # 2 07df - alpha value for color key # 3 TW8823 ? tft flat panel controller techwell, inc. 90 rev a 11/20/2009 osd interrupt enable, vertical active status index (hex) 7 6 5 4 3 2 1 0 reset value 07f0 - - disp_ate osd_ate win4_at - win1_at win0_at 07f1 osd_w_ mask0 osd_w_ mask1 disp_ate _mask osd_ate _mask - - - - f0h main/sub path osd selection index (hex) 7 6 5 4 3 2 1 0 reset value 07f8 - - sub_sel - - main_sel external osd index (hex) 7 6 5 4 3 2 1 0 reset value 08f2 eosd_m ode eosd_vs _pol eosd_hs _pol eosd_ck _pol eosddelay [2:0] osd_por ten 08f3 eosd_hs_pw [5:0] exsync_ sel exhact_ sel 08f4 - ocktps - - - - 08f5 ena_ea_ pin - - ext_alpha [4:0] 08f6 - eoden_dly [2:0] - - - - 08f7 - - - eosd_vs_pw [3:0] TW8823 ? tft flat panel controller techwell, inc. 91 rev a 11/20/2009 lcdc C gamma & dither & key (waver_top) index (hex) 7 6 5 4 3 2 1 0 reset value 0900 gamae_r gamae_g gamae_b - auto_inc gamma_rgb_indx 00h 0901 gamma_ram_starting_addr 00h 0902 - - - - - - gamma_ram_data[9:8] 00h 0903 gamma_ram_data[7:0] 00h 0910 <- 0917 - dither_option - dither_format 00h 0920 <- 0928 rdkeypos_x[7:0] 0921 <- 0929 rdkeypos_y[7:0] 0922 <- 092a - rdkeypos_y[10:8] rdkeypos_x[11:8] 0923 <- 092b keyrdr 0924 <- 092c keyrdg 0925 <- 092d keyrdb lcdc C tga & power management index (hex) 7 6 5 4 3 2 1 0 reset value 0970 - fpdeah fphsah fpvsah rvfpck rvhilo rvbit fpclkc 40h 0971 - - - - - fp ck outdly 00h 0987 - - pwmen pwmal - - 00h 0988 pwm_cnt [7:0] 00h 0989 - - - - - - 00h 098a pwm_clk_div[9:0] 00h 098b - - pwm2en pwm2al - - 00h 098c pwm2_cnt [7:0] 00h 098d - - - - - - 00h 098e pwm2_clk_div[9:0] 00h 09f5 - - - - - enbias efpif efpwr 00h TW8823 ? tft flat panel controller techwell, inc. 92 rev a 11/20/2009 lcdc C tcon index (hex) 7 6 5 4 3 2 1 0 reset value 0a00 - tcck_ph roe_en tcons div_ck 00h 0a01 - rev_en - inv_sel 00h 0a02 - top_btm lft_rht 03h 0a03 pol_co n rck_p roe_p rsp_p clp_p csp_p 07h 0a04 pgm_r ck pgm_ro e pgm_rs p pgm_pol pgm_clp pgm_cs p 34h 0a05 - 00h 0a06 frc_dac_inv rev_sel anal_lc d 02h 0a0a kp_sel kp_ena rsp_width - company 02h 0a0b revv_revc 4dh 0a0c - v_st[11:8] 00h 0a0d v_st[7:0] 00h 0a0e - v_ed[11:8] 02h 0a0f v_ed[7:0] 94h 0a10 cp_sw[11:8] 00h 0a11 cp_sw[7:0] 00h 0a12 - clp_st[11:8] 00h 0a13 clp_st[7:0] 24h 0a14 - clp_ed[11:8] 00h 0a15 clp_ed[7:0] 02h 0a1a - csp_st[11:8] 00h 0a1b csp_st[7:0] 3ch 0a1c - csp_ed[11:8] 00h 0a1d csp_ed[7:0] 01h 0a20 - rck_st[11:8] 00h 0a21 rck_st[7:0] 64h 0a22 - rck_ed[11:8] 01h 0a23 rck_ed[7:0] f4h 0a24 - rsp_st[11:8] 00h 0a25 rsp_st[7:0] 37h 0a26 - rsp_ed[11:8] 00h 0a27 rsp_ed[7:0] 01h 0a2c - roe_st[11:8] 00h 0a2d roe_st[7:0] 0ah 0a2e - roe_ed[11:8] 00h 0a2f roe_ed[7:0] 36h 0a34 - sharp_str_h 00h 0a35 sharp_str_l 20h 0a36 - sharp_end_h 01h 0a37 sharp_end_l e2h 0a38 clpfb - clpw[1:0] - clpsel[2:0] 15h 0a39 - cspw[1:0] - cspsel[2:0] 01h 0a3a - pol_h_ ena pol_h_v al pol_step[3:0] 00h 0a3d - trsp_step[5:0] 00h TW8823 ? tft flat panel controller techwell, inc. 93 rev a 11/20/2009 0a3f - line_co n sync_con[1:0] delta_li ne_con delta_li ne_en 00h TW8823 ? tft flat panel controller techwell, inc. 94 rev a 11/20/2009 TW8823 ? tft flat panel controller techwell, inc. 95 rev a 11/20/2009 lcdc C input measurement index (hex) 7 6 5 4 3 2 1 0 reset value 0b00 - - - - - 00h 0b01 mea_win_h_st [10:0] 20h 0b02 - - - - 01h 0b03 mea_win_h_len [11:0] e0h 0b04 - - - - - 00h 0b05 mea_win_v_st [10:0] 20h 0b06 - - - - - 00h 0b07 mea_win_v_len [10:0] dah 0b08 meas_sel - field_sel rd_lock startm 00h 0b09 - noise_mask [2:0] err_toler [2:0] endet 00h 0b0a threshold_for_act_det [3:0] enalu nofsel [1:0] de_mea 30h 0b0b - - 0b0c - - 0b0d - - 0b0e - - 0b0f - - 0b10 - - - - 0b11 phase_r [28:0] - 0b12 - 0b13 - 0b14 - - - - 0b15 phase_g [28:0] - 0b16 - 0b17 - 0b18 - - - - 0b19 phase_b [28:0] - 0b1a - 0b1b - 0b1c min_r [7:0] - 0b1d min_g [7:0] - 0b1e min_b [7:0] - 0b1f max_r [7:0] - 0b20 max_g [7:0] - 0b21 max_b [7:0] - 0b22 - - - - - - 0b23 v_period [10:0] - 0b24 - 0b25 h_period [15:0] - 0b26 - - - - - 0b27 h_rise_to_fall [11:0] - 0b28 - - - - - 0b29 h_rise_to_act_end [11:0] - 0b2a - - - - - - 0b2b v_rise_to_fall [10:0] - 0b2c - - - - - 0b2d v_rise_to_fall [11:0] - 0b2e - - - - - 0b2f h_act_st_min [11:0] - 0b30 - - - - - 0b31 h_act_st_max [11:0] - TW8823 ? tft flat panel controller techwell, inc. 96 rev a 11/20/2009 0b32 - - - - - 0b33 h_act_end_min [11:0] - 0b34 - - - - - 0b35 h_act_end_max [11:0] - 0b36 - - - - - - 0b37 v_act_st_1 [10:0] - 0b38 - - - - - - 0b39 v_act_st_2 [10:0] - 0b3a - - - - - - 0b3b v_act_end_1 [10:0] - 0b3c - - - - - - 0b3d v_act_end_2 [10:0] - 0b3e - - 0b3f - - 0b40 lum_min [7:0] - 0b41 lum_max [7:0] - 0b42 lum_ave [7:0] - 0b43 - - - - 0b44 v_period_27mh [20:0] - 0b45 - lcdc C ddr memory control index (hex) 7 6 5 4 3 2 1 0 reset value 0c00 - ddr_dqs_sel0 00h 0c01 - ddr_dqs_sel1 00h 0c02 ddr_clko_sel ddr_clk90_sel 28h 0c03 dll_tst_sel - dll_tst dll_tap_s 00h 0c04 dll_rstn - - - - 00h 0c05 rd_ph - ddr_dqs_dly ddr_wrnop 08h 0c06 ddr_t_rc ddr_t_ras a7h 0c07 ddr_t_rfc - ddr_t_rp b4h 0c08 - ddr_t_rcd - ddr_t_wr 43h 0c09 - ddr_refresh init_byp ddr_b_length 03h 0c0a ddr_tst ddr_cas_lat samsng - 70h 0c0b ddr_wtr ddr_btyp ddr_dvst dll_en - ddr_size 11h 0c0c ddr_rstn - - - - - - 00h 0c0d - - - - - - - - - 0c0e - - - - - - - - - 0c0f - - - - - - - - - TW8823 ? tft flat panel controller techwell, inc. 97 rev a 11/20/2009 lcdc C aux control index (hex) 7 6 5 4 3 2 1 0 reset value 0cf0 aux_rwdata 00h 0cf1 - 00h 0cf2 aux_addr[23:16] 00h 0cf3 aux_addr[15:8] 00h 0cf4 aux_addr[7:0] 00h 0cf5 - aux_length[10:8] 00h 0cf6 aux_length[7:0] 00h 0cf7 - - aux_rd aux_wr 00h TW8823 ? tft flat panel controller techwell, inc. 98 rev a 11/20/2009 ccfl and ledc control index (hex) 7 6 5 4 3 2 1 0 reset value 0d00 - - - - - - - biasctl 00h 0d01 oven oien uien fben lockv lockh ccflenb ccflden f2h 0d02 lvt lilt lit adh 0d03 ledc_di g_en ledc_ap dwn ccfl_le dc_st lstp 04h 0d04 fpwm 70h 0d05 fdim 84h 0d06 - ddim[6:0] 00h 0d07 pwmtop 04h tsc (touch screen control) index (hex) 7 6 5 4 3 2 1 0 reset value 0d10 pd_tsc rst_tsc start_o rg penqst rdyqst a[2:0] 80h 0d11 rsyinte nb peninte nb r_sel[2:0] testadc[2:0] 00h 0d12 r0_dout[11:4] 00h 0d13 - - - - r0_dout[3:0] 00h 0d14 - - - - contsa mp clksel[2:0] 00h lcdc : lvds index (hex) 7 6 5 4 3 2 1 0 reset value 0d40 ctlmapping bitperpx[1:0] lvds_op fab_tst lcd_tst 00h 0d41 sel_rd_ sh swap_c h mx_rev_ dcb rev_bit dcb_pol dcb dual mx_sel 00h 0d42 cp_sel[1:0] lp_sel[1:0] - - sel_lvds[1:0] 00h TW8823 ? tft flat panel controller techwell, inc. 99 rev a 11/20/2009 lcdc : remocon rx index (hex) 7 6 5 4 3 2 1 0 reset value 0da0 - rempol htref htini[8] 66h 0da1 htini[7:0] b0h 0da2 - - - - - - - remen 00h 0da3 - - - - remerr or_flag updlint_ flag updint_f lag htint_fl ag 0da4 - - htctrl htsystem 0da5 - - htcommand 0da6 updreg[31:24] 0da7 updreg[23:16] 0da8 updreg[15:8] 0da9 updreg[7:0] 0daa - - - - - - - rempi 0dab remclkref[15:8] 00h 0dac remclkref[7:0] 27h 0dad - - - - upden hten usample[9:8] 0ch 0dae usample[7:0] 1bh 0daf - - - - - - ulleader[9:8] 00h 0db0 ulleader[7:0] 36h 0db1 - - - - - - uhleader[9:8] 00h 0db2 uhleader[7:0] 36h lcdc C lopor index (hex) 7 6 5 4 3 2 1 0 reset value 0dc0 - - - - - - - pd_lso 00h 0dc1 - lvdetlvl[1:0] disdlypor pd_por 00h TW8823 ? tft flat panel controller techwell, inc. 100 rev a 11/20/2009 lcdc C pll (panel clock) index (hex) 7 6 5 4 3 2 1 0 reset value 0dd0 ip_p [2:0] edge_sel _p freq_p[19:1 6 ] 80h 0dd1 freq_p[1 5 : 8 ] 00h 0dd2 freq_p[ 7 :0] 00h 0dd3 ssfreq_p[7:0] 00h 0dd4 ssg_p [3:0] vco_p [1:0] post_p [1:0] 00h 0dd5 pd_p - cpx4_p lpx4_p lpx8_p 00h 0dd6 - - - - - dgain_p[2:0] 00h lcdc C pll (memory clock) index (hex) 7 6 5 4 3 2 1 0 reset value 0dd8 ip_ m[2:0] edge_sel _m freq_ m [19:1 6 ] 80h 0dd9 freq_ m [1 5 : 8 ] 00h 0dda freq_ m [ 7 :0] 00h 0ddb ssfreq_ m [7:0] 00h 0ddc ssg_ m [3:0] vco_ m [1:0] post_ m [1:0] 00h 0ddd pd_m - cpx4_ m lpx4_ m lpx8_ m 00h 0dde dgain_m[2:0] 00h lcdc C dac index (hex) 7 6 5 4 3 2 1 0 reset value 0de0 dacgain dac_vcm dacpd 00h mcu index (hex) 7 6 5 4 3 2 1 0 reset value 0f00 - spi_rd_mode 00h 0f01 - mcu_ck_rg - mcu_ck_div_rg 06h 0f02 - spi_ck_rg - spi_ck_div_rg 06h 0f03 mode_rg 40h 0f04 - busy_ch eck dma_mode 00h 0f05 dma_wait 80h 0f06 dma_reg_page 06h 0f07 index 00h 0f08 dma_length[15:8] 00h 0f09 dma_length[7:0] 00h 0f0a wr_reg1_rg 00h 0f0b wr_reg2_rg 00h 0f0c wr_reg3_rg 00h TW8823 ? tft flat panel controller techwell, inc. 101 rev a 11/20/2009 0f0d wr_reg4_rg 00h 0f0e wr_reg5_rg 00h 0f0f clk_switch_wait 1fh 0f10 default r/w buffer1 00h 0f11 default r/w buffer2 00h 0f12 default r/w buffer3 00h 0f13 default r/w buffer4 00h 0f14 default r/w buffer5 00h 0f15 default r/w buffer6 00h 0f16 default r/w buffer7 00h 0f17 default r/w buffer8 00h 0f18 status_cmd_rg 05h 0f19 - busy_po l busy_sel[2:0] 08h 0f1a dma_length[23:16] 00h 0f20 mcu status chip reset osd dma - rg_spi_ en cache_e n_rg bootsel mcu reset 08h 0f21 isp passcode write port 00h 0f22 rg_dvidt0[15:8] 00h 0f23 rg_dvidt0[7:0] 90h 0f24 rg_dvidt1[15:8] 00h 0f25 rg_dvidt1[7:0] 90h 0f26 rg_dvidt2[15:8] 00h 0f27 rg_dvidt2[7:0] 90h 0f28 rg_dvidt3[15:8] 00h 0f29 rg_dvidt3[7:0] 0ch 0f2a rg_dvidt4[15:8] 00h 0f2b rg_dvidt4[7:0] 0ch 0f2c osd_wait[7:0] 02h special function register 0x9a rg_pgmbase_adr[7:0] 00h 0xfa int14~int7 flag 00h 0xfb int14~int7 enable 00h 0xfc int14~int7 priority 00h 0xfd int14~int7 edge/level 00h 0xfe int14~int7 edge/level polarity 00h 0xe2 - rg_pdn - 00h 0x80 p0 ffh 0x81 sp 07h 0x82 dpl 00h 0x83 dph 00h 0x84 dpl1 00h 0x85 dph1 00h 0x86 dps 00h 0x87 pcon 00h 0x88 tcon 00h 0x89 tmod 00h TW8823 ? tft flat panel controller techwell, inc. 102 rev a 11/20/2009 0x8a tl0 00h 0x8b tl1 00h 0x8c th0 00h 0x8d th1 00h 0x8e ckcon 07h 0x90 p1 ffh 0x91 eif 00h 0x92 wtst 00h 0x93 dpx0 00h 0x95 dpx1 00h 0x98 scon0 00h 0x99 sbuf0 00h 0xa0 p2 00h 0xa8 ie 00h 0xb0 p3 ffh 0xb8 ip 00h 0xc0 scon1 00h 0xc1 sbuf1 00h 0xc2 ccl1 00h 0xc3 cch1 00h 0xc4 ccl2 00h 0xc5 cch2 00h 0xc6 ccl3 00h 0xc7 cch3 00h 0xc8 t2con 00h 0xc9 t2if 00h 0xca crcl 00h 0xcb crch 00h 0xcc tl2 00h 0xcd th2 00h 0xce ccen 00h 0xd0 psw 00h 0xd8 wdcon 00h 0xe0 acc 00h 0xe8 eie 00h 0xe9 status 00h 0xea mxax 00h 0xeb ta 00h 0xf0 b 00h 0xf8 eip 00h 0xf8 md0 00h TW8823 ? tft flat panel controller techwell, inc. 103 rev a 11/20/2009 global register 0x000 C product id & revision bit function r/w description reset 7-2 prod_id r/w chip id. 010_011 1-0 revsion r/w chip revision number 00 TW8823 ? tft flat panel controller techwell, inc. 104 rev a 11/20/2009 gpio registers 0x040 ~ 0x049 C gpio registers index (hex) bit function r/w description reset 0x040 7-0 gpio_en 0 r/w gpio enable (active high) 00h 0x041 7-0 gpio_en 1 r/w gpio enable (active high) 00h 0x042 7-0 gpio_en 2 r/w gpio enable (active high) 00h 0x043 7-0 gpio_en 3 r/w gpio enable (active high) 00h 0x044 7-0 gpio_en 4 r/w gpio enable (active high) 00h 0x045 7-0 gpio_en 5 r/w gpio enable (active high) 00h 0x046 7-0 gpio_en 6 r/w gpio enable (active high) 00h 0x047 7-0 gpio_en 7 r/w gpio enable (active high) 00h 0x048 7-0 gpio_en 8 r/w gpio enable (active high) 00h 0x049 7-0 gpio_en 9 r/w gpio enable (active high) 00h 0x050 ~ 0x059 C gpio registers index (hex) bit function r/w description reset 0x050 7-0 gpio_oe 0 r/w gpio output enable (active high) 00h 0x051 7-0 gpio_oe 1 r/w gpio output enable (active high) 00h 0x052 7-0 gpio_oe 2 r/w gpio output enable (active high) 00h 0x053 7-0 gpio_oe 3 r/w gpio output enable (active high) 00h 0x054 7-0 gpio_oe 4 r/w gpio output enable (active high) 00h 0x055 7-0 gpio_oe 5 r/w gpio output enable (active high) 00h 0x056 7-0 gpio_oe 6 r/w gpio output enable (active high) 00h 0x057 7-0 gpio_oe 7 r/w gpio output enable (active high) 00h 0x058 7-0 gpio_oe 8 r/w gpio output enable (active high) 00h 0x059 7-0 gpio_oe 9 r/w gpio output enable (active high) 00h 0x060 ~ 0x069 C gpio registers index (hex) bit function r/w description reset 0x060 7-0 gpio_id 0 ro gpio input data 00h 0x061 7-0 gpio_id 1 ro gpio input data 00h 0x062 7-0 gpio_id 2 ro gpio input data 00h 0x063 7-0 gpio_id 3 ro gpio input data 00h 0x064 7-0 gpio_id 4 ro gpio input data 00h 0x065 7-0 gpio_id 5 ro gpio input data 00h 0x066 7-0 gpio_id 6 ro gpio input data 00h 0x067 7-0 gpio_id 7 ro gpio input data 00h 0x068 7-0 gpio_id 8 ro gpio input data 00h 0x069 7-0 gpio_id 9 ro gpio input data 00h TW8823 ? tft flat panel controller techwell, inc. 105 rev a 11/20/2009 0x070 ~ 0x079 C gpio registers index (hex) bit function r/w description reset 0x070 7-0 gpio_od 0 r/w gpio output data 00h 0x071 7-0 gpio_od 1 r/w gpio output data 00h 0x072 7-0 gpio_od 2 r/w gpio output data 00h 0x073 7-0 gpio_od 3 r/w gpio output data 00h 0x074 7-0 gpio_od 4 r/w gpio output data 00h 0x075 7-0 gpio_od 5 r/w gpio output data 00h 0x076 7-0 gpio_od 6 r/w gpio output data 00h 0x077 7-0 gpio_od 7 r/w gpio output data 00h 0x078 7-0 gpio_od 8 r/w gpio output data 00h 0x079 7-0 gpio_od 9 r/w gpio output data 00h 0x080 C test gpo bit function r/w description reset 7-4 * r/w reserved 00h 3 tgpo_en r/w test gpo enable for pin 202 0h 2-0 tgpo_sel r/w test gpo select for signal through pin 202 0 : vdloss 1 : field 2 : pwm 3 : lso clock 4 : pen irq 5 : osd win active 6 : osd win active 7 : mbist test pass 00h 0x090 ~ 0x099 C pull down & up registers index (hex) bit function r/w description reset 0x090 7-0 pullud_en_0 r/w ffh 0x091 7-0 pullud_en_1 r/w ffh 0x092 7-0 pullud_en_2 r/w ffh 0x093 7-0 pullud_en_3 r/w f3h 0x094 7-0 pullud_en_4 r/w ffh 0x095 7-0 pullud_en_5 r/w ffh 0x096 7-0 pullud_en_6 r/w ffh 0x097 7-0 pullud_en_7 r/w mcu_en 0 : 3fh mcu_en 1 : ffh 0x098 7-0 pullud_en_8 r/w mcu_en 0 : c0h mcu_en 1 : ffh 0x099 7-0 pullud_en_9 r/w f3h TW8823 ? tft flat panel controller techwell, inc. 106 rev a 11/20/2009 0x0a0 C mode status bit function r/w description reset 7 por r reset from low power detection 0: reset 1: normal status 1 6 i2c_cs r i2c chip address select 0 : i2c chip address 88 1 : i2c chip address 8c value of ?pin 045? when ?pin 143?(reset) is low 7 mcu_en r mcu enable 0: internal mcu disable 1: internal mcu enable value of ?pin 191? when ?pin 143?(reset) is low 6 host r mode for host parallel interface 0: intel mode 1: non intel mode value of ?pin 145? when ?pin 143?(reset) is low 7 boot_sel r mcu boot from 0: spi 1: internal rom value of ?pin 145? when ?pin 143?(reset) is low 6 h_csl r chip select when host parallel interface mode value of ?pin 192? 7 pwr_dn r power down for xtal clock from pin ?pwr _dn? value of ?pin 142? 6 test r production test mode from pin ?test? value of ?pin 144? TW8823 ? tft flat panel controller techwell, inc. 107 rev a 11/20/2009 0x0a1 C dtv input mode bit function r/w description reset 7-6 dual_dtv r/w dual dtv input mode 00: only dtv1 - dtv1 : 24b/16b/8b601/8b656 - dtv2 : no used 01: dual dtv mode - dtv1 : 16b/8b601/8b656 - dtv2 : 8b656 10: dual dtv mode - dtv1 : 565(rgb) - dtv2 : 8b656 11: dual dtv mode - dtv1 : 666(rgb) - dtv2 : 8b656 0 5-1 * r/w 0 0 sacnt r/w i2c index auto-increment enable 0: non-auto mode 1: auto mode 0 0x0aa - 0x0ad C clock control 0x0aa C clock control option bit function r/w description reset 7 ext_pclk r/w external clock use for panel clock 0 6 ext_mclk r/w external clock use for memory clock 0 2-1 pck_cap r/w panel out clock pin (fpclk) drive c apability 00 : 8ma 01 : 4ma 10 : 12ma 11 : 12ma 0 0x0ab C clock polarity bit function r/w description reset 7 ckpol_dbl r/w clock polarity for pclk of double p ixel mode 0 6 ckpol_dtv1 r/w clock polarity for dtv1 clock 0 5 ckpol_dtv2 r/w clock polarity for dtv1 clock 0 4 ckpol_sys r/w clock polarity for system clock 0 3 ckpol_p r/w clock polarity for panel clock 0 2 ckpol_pdv r/w clock polarity for panel clock of dual view mode 0 1 ckpol_m r/w clock polarity for memory clk 0 0 ckpol_z r/w clock polarity for panel clock of zoo m-by-pass mode 0 TW8823 ? tft flat panel controller techwell, inc. 108 rev a 11/20/2009 0x0ac : clock polarity bit function r/w description reset 7-2 * r/w reserved 0 1 ckpol_dec r/w clock polarity for decoder clock 0 0 ckpol_main r/w clock polarity for main path clock 0 0x0ad : clock power down bit function r/w description reset 7 clkpd_all r/w clock power down for all clock 0 6 ckpd_dtv1 r/w clock power down for dtv1 clock 0 5 ckpd_dtv2 r/w clock power down for dtv1 clock 0 4 ckpd_sys r/w clock power down for system clock 0 3 ckpd_p r/w clock power down for panel clock 0 2 ckpd_pdv r/w clock power down for panel clock of dual view mode 0 1 ckpd_m r/w clock power down for memory clk 0 0 * r/w reserved 0 TW8823 ? tft flat panel controller techwell, inc. 109 rev a 11/20/2009 status & interrupt 0x0b0 to 0x0ba C status and interrupt registers 0x0b0 C status register bit function r/w description reset 7 line buffer over flow r this bit is set if the fp clock count exceeds the maximum number in between two consecutive fphs pulses for the even field, cleared by writing back a "1". 0 6 line buffer under flow r this bit is set if the fp clock count exceeds the maximum number in between two consecutive fphs pulses for the odd field, cleared by writing back a "1". 0 5 input vsync loss status changed r this bit is set when the status bit of "input vsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 input hsync loss status changed r this bit is set when the status bit of "input hsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 video input status changed indication r vdloss status bit change (register 1 bit 7) or de t50 status bit change (register 1 bit 0) write a one to this bit to reset. 0 2 input vsync loss r this bit is set when the input vsync pulse is los t, reset by re-appearance of vsync. an 11-bit counter is used for vsync period measurem ent. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 input hsync loss r this bit is set when the input hsync pulse is los t, reset by re-appearance of hsync. an 11- bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0 sync detect status r logic function of: inverted ?bit 1? anding with inverted ?bit 2? 0x0b1C status register bit function r/w description reset 7 input measurement data ready r this bit is set when the measurement data is read y for readout, reset when a new "startm" is set. 0 6 power state changed r this bit is set when the power management state h as changed, reset by writing back a "1". 0 5 input vsync period change detected r this bit is set when the input vsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the vsync period is measured fo r every frame. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 4 input hsync period change detected r this bit is set when the input hsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the hsync period is measured fo r every scan line. if the difference from the last measurement result stored in the registers , is larger than the error tolerance, the hsync period is considered to have changed. 0 3 line buffer overflow or underflow r 0 2 vdccdet r high if there is a change in vdloss or det50 or ccvalid 0 1 vloss/ hloss status changed r this bit reflects the ?or? condition of status bi t index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0 "sync detect status" changed r this bit is set when the status bit of "sync dete ct status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or b y resetting the "endet" bit. 0 TW8823 ? tft flat panel controller techwell, inc. 110 rev a 11/20/2009 0x0b2C interrupt control register bit function r/w description reset 7 irq_b_b17 r/w enable/disable 0x0b1 bit 7 as an ir q source 0: enable 1: disable 1 6 irq_b_b16 r/w enable/disable 0x0b1 bit 6 as an ir q source 0: enable 1: disable 1 5 irq_b_b15 r/w enable/disable 0x0b1 bit 5 as an ir q source 0: enable 1: disable 1 4 irq_b_b14 r/w enable/disable 0x0b1 bit 4 as an ir q source 0: enable 1: disable 1 3 irq_b_b13 r/w enable/disable 0x0b1 bit 3 as an ir q source 0: enable 1: disable 1 2 irq_b_b12 r/w enable/disable 0x0b1 bit 2 as an ir q source 0: enable 1: disable 1 1 irq_b_b11 r/w enable/disable 0x0b1 bit 1 as an ir q source 0: enable 1: disable 1 0 irq_b_b10 r/w enable/disable 0x0b1 bit 0 as an ir q source 0: enable 1: disable 1 0x0b3 C interrupt control register bit function r/w description reset 7-3 - r/w reserved 00h 2 irq_b_bd r/w enable/disable vdloss as an irq sour ce 0: enable 1: disable 1 1 irq_b_cc r/w reserved 1 0 irq_b_50 r/w enable/disable det50 as an irq sourc e 0: enable 1: disable 1 TW8823 ? tft flat panel controller techwell, inc. 111 rev a 11/20/2009 0x0b4 C status register bit function r/w description reset 7 line buffer over flow r same as 0x0b0[7] 0 6 line buffer under flow r same as 0x0b0[6] 0 5 pip input vsync loss status changed r this bit is set when the status bit of "input vsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 pip input hsync loss status changed r this bit is set when the status bit of "input hsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 video input status changed indication r/w same as 0x0b0[3] 0 2 pip input vsync loss r this bit is set when the input vsync pulse is los t, reset by re-appearance of vsync. an 11-bit counter is used for vsync period measurem ent. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 pip input hsync loss r this bit is set when the input hsync pulse is los t, reset by re-appearance of hsync. an 11- bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0 pip sync detect status r logic function of: inverted ?bit 1? anding with inverted ?bit 2? 0x0b5 C status register bit function r/w description reset 7 input measurement data ready r same as 0x0b1[7] 0 6 power state changed r same as 0x0b1[6] 0 5 pip input vsync period change detected r this bit is set when the input vsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the vsync period is measured fo r every frame. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 4 pip input hsync period change detected r this bit is set when the input hsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the hsync period is measured fo r every scan line. if the difference from the last measurement result stored in the registers , is larger than the error tolerance, the hsync period is considered to have changed. 0 3 line buffer overflow or underflow r same as 0x0b1[3] 0 2 vdccdet r same as 0x0b1[2] 0 1 pip vloss/ hloss status changed r this bit reflects the ?or? condition of status bi t index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0 pip "sync detect status" changed r this bit is set when the status bit of "sync dete ct status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or b y resetting the "endet" bit. 0 TW8823 ? tft flat panel controller techwell, inc. 112 rev a 11/20/2009 0x0b6 C status register bit function r/w description reset 7 line buffer over flow r same as 0x0b0[7] 0 6 line buffer under flow r same as 0x0b0[6] 0 5 mpip input vsync loss status changed r this bit is set when the status bit of "input vsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 4 mpip input hsync loss status changed r this bit is set when the status bit of "input hsy nc loss" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or by resetting the "endet" bit. 0 3 video input status changed indication r/w same as 0x0b0[3] 0 2 mpip input vsync loss r this bit is set when the input vsync pulse is los t, reset by re-appearance of vsync. an 11-bit counter is used for vsync period measurem ent. if this counter overflows 4 times, the vsync is considered to be lost. 0 1 mpip input hsync loss r this bit is set when the input hsync pulse is los t, reset by re-appearance of hsync. an 11- bit counter is used for hsync period measurement. if this counter overflows 4 times, the hsync is considered to be lost. 0 0 mpip sync detect status r logic function of: inverted ?bit 1? anding with inverted ?bit 2? 0x0b7 C status register bit function r/w description reset 7 input measurement data ready r this bit is set when the measurement data is read y for readout, reset when a new "startm" is set. 0 6 power state changed r same as 0x0b1[6] 0 5 mpip input vsync period change detected r this bit is set when the input vsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the vsync period is measured fo r every frame. if the difference from the last measurement result stored in the registers, is larger than the error tolerance, the vsync period is considered to have changed. 0 4 mpip input hsync period change detected r this bit is set when the input hsync period is ch anged, reset when "endet" is cleared. when "endet" bit is set, the hsync period is measured fo r every scan line. if the difference from the last measurement result stored in the registers , is larger than the error tolerance, the hsync period is considered to have changed. 0 3 line buffer overflow or underflow r same as 0x0b1[3] 0 2 vdccdet r same as 0x0b1[2] 0 1 mpip vloss/ hloss status changed r this bit reflects the ?or? condition of status bi t index b0 bit 5 (vloss status changed) and index b0 bit 4 (hloss status changed). 0 0 mpip "sync detect status" changed r this bit is set when the status bit of "sync dete ct status" had changed, either 1 to 0 or 0 to 1. this bit is cleared by writing back a "1", or b y resetting the "endet" bit. 0 TW8823 ? tft flat panel controller techwell, inc. 113 rev a 11/20/2009 0x0b8 C interrupt mask register bit function r/w description reset 7- 6 measurement input selection r/w 0,1: main, 2: pip, 3: mpip 00 5 irq_1b5_5 r/w 0: enable 0x0b5[5] as an irq source 0 4 irq_1b5_4 r/w 0: enable 0x0b5[4] as an irq source 0 3 - 2 - r/w reserved 00 1 irq_1b5_1 r/w 0: enable 0x0b5[1] as an irq source 0 0 irq_1b5_0 r/w 0: enable 0x0b5[0] as an irq source 0 0x0b9 C interrupt mask register bit function r/w description reset 7- 6 - r/w reserved 00 5 irq_1b7_5 r/w 0: enable 0x0b7[5] as an irq source 0 4 irq_1b7_4 r/w 0: enable 0x0b7[4] as an irq source 0 3 - 2 - r/w reserved 00 1 irq_1b7_1 r/w 0: enable 0x0b7[1] as an irq source 0 0 irq_1b7_0 r/w 0: enable 0x0b7[0] as an irq source 0 0x0ba C irq bit function r/w description reset 7 irq_oe r/w irq output enable 0 6 irq_al r/w irq active low 0 5 irq_st r/w irq status 0 4-0 * r/w reserved 00 TW8823 ? tft flat panel controller techwell, inc. 114 rev a 11/20/2009 internal test 0x0c6 C internal test control bit function r/w description reset 7 selc r/w select c as for test data out 0 6 * r/w reserved 0 5 data_zero set with rgb data all ?0? 0 4-0 * r/w reserved 00 0x0c7 C test mode bit function r/w description reset 7-0 bwymin r bwymin - 0x0c8 C test mode bit function r/w description reset 7-0 bwymax r bwymax - 0x0c9 C test mode bit function r/w description reset 7-0 bwfmin r bwfmin - 0x0ca C test mode bit function r/w description reset 7-0 bwfmax r bwfmax - 0x0cb C test mode bit function r/w description reset 7-0 bwbtilt r bwbtilt - 0x0cc C test mode bit function r/w description reset 7-0 bwwtilt r bwwtilt - TW8823 ? tft flat panel controller techwell, inc. 115 rev a 11/20/2009 0x0ce C internal test mode bit function r/w description reset 7-0 test_ mode r/w test_mode this register is reserved for testing purpose. in n ormal operation, only 0 should be written into this register. 03h = digital video decoder & rgb mix direct input test this test mode allows digital data to be input from dtvd[23:0] pins to the input of the d igital logic of the video decoder (replaces ycadc output) as the case when the conten ts of this register is 04h. besides this, the fpg1/fpb1/fpr1 pins become inputs and provide data in place of rgbadc data output. 04h = digital video decoder direct input test this test mode allows digital data to be input from dtvd pins to the input of the digital logic of the video decoder. (replaces adc output) dtvd(23-16) > ?y? decoder input data, dtvd(15- 8) > ?u? decoder input data dtvd(7-0) > ?v? decoder input data 05h = closed caption test mode. 06h = ycadc test mode (dtvd pins become outputs) yc adc digital output is made available externally. ?y? adc output data > dtvd(15-8), ?c? & ?fb? ad c output data > dtvd(7-0) index-63-bit-7 = 1 > ?c? data index-63-bit -7 = 0 > ?fb? data. 07h = digital video decoder output test (dtvd pins become outputs) the output of the digital video decoder output is available externall y. ?r? decoder out data > dtvd(23-16), ?g? decoder out data > dtvd(15-8) ?b? decoder out data > dtvd(7-0) ?vsync? > clamp ?hsync? > gpio[1] ?hactiv e? > gpio[0] 08h = rgbadc test mode (dtvd pins become outputs) r gbadc digital output is made available externally. ?g? adc output data > dtvd(15-8), ?b? & ?r? adc o utput data > dtvd(7-0) index-63-bit-7 = 1 > ?b? data index -63-bit-7 = 0 > ?r? data. 09h = dac test mode. dtvd[7:0] inputs are routed to the dac data input ?din?. 11h = tw88 internal node to flat panel output 00h 0x0e0 C s/w reset bit function r/w description reset 7 sw_rst r/w chip software reset (self clear bit) 0 6-0 * r/w reserved 00 TW8823 ? tft flat panel controller techwell, inc. 116 rev a 11/20/2009 decoder 0x0101 C chip status register (cstatus) bit function r/w description reset 7 vdloss r 1 = video not present. (sync is not det ected in a number of consecutive video lines specif ied by misscnt register) 0 = video detected. - 6 hlock r 1 = horizontal sync pll is locked to the incoming video source. 0 = horizontal sync pll is not locked. - 5 slock r 1 = sub-carrier pll is locked to the inco ming video source. 0 = sub-carrier pll is not locked. - 4 field r 0 = odd field is being decoded. 1 = even field is being decoded. - 3 vlock r 1 = vertical logic is locked to the incom ing video source. 0 = vertical logic is not locked. - 2 reserved - reserved - 1 mono r 1 = no color burst signal detected. 0 = color burst signal detected. - 0 det50 r 1 = 50hz source detected 0 = 60hz source detected the actual vertical scanning frequency depends on t he current standard invoked. - 0x0102 C input format (inform) bit function r/w description reset 7,3-2 ysel[2:0] r/w these three bits control the y input video selection mux. 0 = yin0 1 = yin1 2 = yin2 3 = yin3 others = n/a 0 6 fc27 r/w 1 = input crystal clock frequency is 27m hz. 0 = square pixel mode. must use 24.54mhz for 60hz f ield rate source or 29.5mhz for 50hz field rate source. 1 5-4 ifsel r/w 0 = composite video decoding 1 = s-video decoding 2 = component video decoding (for 480i / 576i input only) 3 = reserved 0 1 csel r/w this bit controls the c input source sel ection. 0 = cin0 1 = cin1 0 0 reserved - reserved - TW8823 ? tft flat panel controller techwell, inc. 117 rev a 11/20/2009 0x0103 C reserved bit function r/w description reset 7-0 reserved - reserved - 0x0104 C ckhy bit function r/w description reset 7 reserved - reserved - 6-5 ckhy r/w color killer time constant 0 = fast 3 = slow 0 4-0 reserved - reserved - 0x0105 C reserved bit function r/w description reset 7-0 reserved - reserved - 0x0106 C analog control register (acntl) bit function r/w description reset 7 sreset w a 1 written to this bit resets the devic e to its default state but all register content rem ains unchanged. this bit is self-resetting. 0 6 pdmix r/w power down for mix 0 5 fbyp r/w 0 = anti-alias filter enable 1 = bypass 0 4 agc_enb r/w 0 = agc loop function enabled. 1 = agc loop function disabled. gain is set to by a gcgain. 0 3 clk_pdn r/w 0 = normal clock operation. 1 = 27 mhz clock in power down mode. 0 2 y_pdn r/w 0 = luma adc in normal operation. 1 = luma adc in power down mode. 0 1 c_pdn r/w 0 = chroma adc in normal operation. 1 = chroma adc in power down mode. 0 0 v_pdn r/w 0 =v channel adc in normal operation. 1 = v channel adc in power down mode. 0 0x0107 C cropping register, high (crop_hi) bit function r/w description reset 7-6 vdelay_hi r/w these bits are bit 9 to 8 of the 10-bit vertical delay register. - 5-4 vactive_hi r/w these bits are bit 9 to 8 of the 10-bit vactive register. refer to description on r eg09 for its shadow register. - 3-2 hdelay_hi r/w these bits are bit 9 to 8 of the 10-bit horizontal delay register. - 1-0 hactive_hi r/w these bits are bit 9 to 8 of the 10-bit hactive register. - TW8823 ? tft flat panel controller techwell, inc. 118 rev a 11/20/2009 0x0108 C vertical delay register, low (vdelay_lo) bit function r/w description reset 7-0 vdelay_lo r/w these bits are bit 7 to 0 of the 10-bit vertical delay register. the two msbs are in the crop_hi register. it defines the number of lines be tween the leading edge of vsync and the start of the active video. 15 0x0109 C vertical active register, low (vactive_lo) bit function r/w description reset 7-0 vactive_lo r/w these bits are bit 7 to 0 of the 10-bit vertical active register. the two msbs are in the crop_hi register. it defines the number of active v ideo lines per frame output. the vactive register has a shadow register for use with 50hz source when atreg of reg0x1c is not set. this register can be accessed t hrough the same index address by first changing the format standard to any 50hz standard. - 0x010a C horizontal delay register, low (hdelay_lo) bit function r/w description reset 7-0 hdelay_lo r/w these bits are bit 7 to 0 of the 10-bit horizontal delay register. the two msbs are in the crop_hi register. it defines the number of pixels b etween the leading edge of the hsync and the start of the image cropping for active vide o. the hdelay_lo register has two shadow registers for use with pal and secam sources respectively. these registers can be accessed using the same index address by first changing the decoding format to the corresponding s tandard. - 0x010b C horizontal active register, low (hactive_l o) bit function r/w description reset 7-0 hactive_lo r/w these bits are bit 7 to 0 of the 10-bit horizontal active register. the two msbs ar e in the crop_hi register. it defines the number of active p ixels per line output. d0 0x010c C control register i (cntrl1) bit function r/w description reset 7 pbw r/w 1 = wide chroma bpf bw 0 = normal chroma bpf bw 1 6 dem r/w false color reduction mode for secam. 1 = on 0 = off 0 5 palsw r/w 1 = pal switch sensitivity low 0 = pal switch sensitivity normal 0 4 set7 r/w 1 = the black level is 7.5 ire above the blank level 0 = the black level is the same as the blank level 0 3 comb r/w 1 = adaptive comb filter on for ntsc/pal 0 = notch filter 1 2 hcomp r/w 1 = operation mode 1 (recommended) 0 = operation mode 0 1 1 ycomb r/w comb filter operation in monochrome mod e 1 = off 0 = on 0 0 pdly r/w pal delay line 1 = disable 0 = enable 0 TW8823 ? tft flat panel controller techwell, inc. 119 rev a 11/20/2009 0x0110 C brightness control register (bright) bit function r/w description reset 7-0 brightness r/w these bits control the brightnes s. they have value of ?128 to 127 in 2's complement form. positive value increases brightness. a value 0 has no effect on the data. 00 0x0111 C contrast control register (contrast) bit function r/w description reset 7-0 contrast r/w these bits control the luminance c ontrast gain. a value of 100 (64h) has a gain of 1. the range of adjustment is from 0% to 255% at 1% pe r step. 60 0x0112 C sharpness control register i (sharpness) bit function r/w description reset 7 scurve r/w this bit controls the center frequency of the peaking filter. the corresponding gain adjustment is hflt. 0 = low 1 = center 0 6 reserved - reserved - 5-4 cti r/w color transient improvement level contr ol. there are 4 enhancement levels with 0 being the lowest and 3 being the highest. 1 3-0 sharp r/w these bits control the amount of shar pness enhancement on the luminance signals. there are 16 levels of control with '0' having no effect on the output image. 1 through 15 provides sharpness enhancement with ?15? being the stronges t. 1 0x0113 C chroma (u) gain register (sat_u) bit function r/w description reset 7-0 sat_u r/w these bits control the digital gain a djustment to the u (or cb) component of the digital video signal. the color saturation can be adjusted by adj usting the u and v color gain components by the same amount in the normal situation. the u a nd v can also be adjusted independently to provide greater flexibility. the r ange of adjustment is 0 to 200%. 80 0x0114 C chroma (v) gain register (sat_v) bit function r/w description reset 7-0 sat_v r/w these bits control the digital gain a djustment to the v (or cr) component of the digital video signal. the color saturation can be adjusted by adj usting the u and v color gain components by the same amount in the normal situation. the u a nd v can also be adjusted independently to provide greater flexibility. the r ange of adjustment is 0 to 200%. 80 0x0115 C hue control register (hue) bit function r/w description reset 7-0 hue r/w these bits control the color hue. they have value from +96 o (7fh) to -96 o (80h) with an increment of 0.75 o . the default value is 0 (00h). this is effective f or ntsc standard only. 00 0x0116 C reserved bit function r/w description reset 7-0 reserved - reserved - TW8823 ? tft flat panel controller techwell, inc. 120 rev a 11/20/2009 0x0117 C vertical peaking control i bit function r/w description reset 7-4 shcor r/w these bits provide coring function fo r the sharpness control. 2 3 reserved - reserved - 2-0 vshp r/w these bits control the vertical peakin g level with '0' being the minimum and '7' being th e maximum. 0 0x0118 C coring control register (coring) bit function r/w description reset 7-6 ctcor r/w these bits control the coring functio n for the cti. it has internal step size of 2. 1 5-4 ccor r/w these bits control the low level corin g function for the cb/cr output. 0 3-2 vcor r/w these bits control the coring function of the vertical peaking logic. it has an internal step size of 2. 1 1-0 cif r/w these bits control the if compensation level. 0 = none 1 = 1.5 db 2 = 3 db 3 = 6 db (secam) 0 0x011c C standard selection (sdt) bit function r/w description reset 7 detstus r 0 = idle 1 = detection in progress - 6-4 stdnow r current standard invoked 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = not valid - 3 atreg r/w 1 = disable the shadow registers. 0 = enable vactive and hdelay shadow registers valu e depending on standard 0 2-0 standard r/w standard selection 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = auto detection 7 TW8823 ? tft flat panel controller techwell, inc. 121 rev a 11/20/2009 0x011d C standard recognition (sdtr) bit function r/w description reset 7 atstart r/w writing 1 to this bit will manually i nitiate the auto format detection process. this bit is a self- resetting bit. 0 6 pal6_en r/w 1 = enable recognition of pal60. 0 = disable recognition. 1 5 paln_en r/w 1 = enable recognition of pal (cn). 0 = disable recognition. 1 4 palm_en r/w 1 = enable recognition of pal (m). 0 = disable recognition. 1 3 nt44_en r/w 1 = enable recognition of ntsc 4.43. 0 = disable recognition. 1 2 sec_en r/w 1 = enable recognition of secam. 0 = disable recognition. 1 1 palb_en r/w 1 = enable recognition of pal (b,d,g, h,i). 0 = disable recognition. 1 0 ntsc_en r/w 1 = enable recognition of ntsc (m). 0 = disable recognition. 1 0x011e C component video format (cvfmt) bit name r/w description reset 7 reserved - reserved - 6-4 cvstd r component video input format detection. 0 = 480i 1 = 576i 2 = 480p 3 = 576p - 3-0 cvfmt r/w component video format selection. 0 = 480i 1 = 576i 2 = 480p 3 = 576p 8 = auto 8 0x011f C adc control register bit name r/w description reset 7-3 reserved - reserved - 2 vref r/w video adc voltage reference control. 0 = normal operation 0 1 iref r/w video adc bias control 0 = normal operation 0 0 save r/w video adc reference current control 0=normal current 1=2/3 of normal curre nt 0 TW8823 ? tft flat panel controller techwell, inc. 122 rev a 11/20/2009 0x0120 C clamping gain (clmpg) bit function r/w description reset 7-4 clpend r/w these 4 bits set the end time of the clamping pulse in the increment of 8 system clocks . this determines the clamping pulse duration together wit h the clpst register. 5 3-0 clpst r/w these 4 bits set the start time of th e clamping pulse in the increment of 8 system clock s. it is referenced to pclamp position. 0 0x0121 C individual agc gain (iagc) bit function r/w description reset 7-4 nmgain r/w these bits control the normal agc lo op maximum correction value. larger value decrease the agc response time. 4 3-1 wpgain r/w peak agc loop gain control. 1 0 agcgain[8] r/w this bit is the msb of the 9-bit r egister that controls the agc gain when agc loop is disabled. 0 0x0122 C agc gain (agcgain) bit function r/w description reset 7-0 agcgain[7:0] r/w these bits are the lower 8 bit s of the 9-bit register that controls the agc gain when agc loop is disabled. f0 0x0123 C white peak threshold (peakwt) bit function r/w description reset 7-0 peakwt r/w these bits control the white peak de tection threshold. d8 0x0124C clamp level (clmpl) bit function r/w description reset 7 clmpld r/w 0 = clamping level is set by clmpl. 1 = clamping level is preset to 60d for 60hz field rate or 63d for 50hz field. 1 6-0 clmpl r/w these bits determine the clamping lev el of the y channel. 3c 0x0125C sync amplitude (synct) bit function r/w description reset 7 synctd r/w 0 = reference sync amplitude is set by synct. 1 = reference sync amplitude is preset to 38h for 6 0hz field rate or 3bh for 50hz field rate. 1 6-0 synct r/w these bits determine the standard syn c pulse amplitude for agc reference. 38 0x0126 C sync miss count register (misscnt) bit function r/w description reset 7-4 misscnt r/w these bits set the threshold for ho rizontal sync miss count threshold. 4 3-0 hswin r/w these bits set the size for the horiz ontal sync detection window. 4 TW8823 ? tft flat panel controller techwell, inc. 123 rev a 11/20/2009 0x0127 C clamp position register (pclamp) bit function r/w description reset 7-0 pclamp r/w these bits set the clamping position from the pll sync edge 2a 0x0128 C vertical control register bit function r/w description reset 7-6 vlcki r/w vertical lock in time. 0 = fastest 3 = slowest. 0 5-4 vlcko r/w vertical lock out time. 0 = fastest 3 = slowest. 0 3 vmode r/w this bit controls the vertical detectio n window. 0 = vertical count down mode 1 = search mode 0 2 detv r/w 0 = normal vsync logic 1 = recommended for special switching application o nly 0 1 afld r/w auto field generation control 0 = off 1 = on 0 0 vint r/w vertical integration time control. 0 = normal 1 = long 0 0x0129 C vertical control ii bit function r/w description reset 7-5 bsht r/w burst pll center frequency control. (r eserved) 0 4-0 vsht r/w vsync output delay control in the incr ement of half line length (reserved) 15 0x012a C color killer level control bit function r/w description reset 7-6 ckilmax r/w these bits control the amount of co lor killer hysteresis. the hysteresis amount is proportional to the value. 2 5-0 ckilmin r/w these bits control the color killer threshold. larger value gives lower killer level. 20 0x012b C comb filter control bit function r/w description reset 7-4 htl r/w adaptive comb filter combing control. f actory use only. 4 3-0 vtl r/w adaptive comb filter combing control. f actory use only. 4 0x012c C luma delay and hsync control bit function r/w description reset 7 cklm r/w color killer mode 0 = norm al 1 = fast (for special applicat ion) 0 6-4 ydly r/w luma delay fine adjustment. this 2's c omplement number provides ?4 to +3 unit delay control. 3 3-0 hflt r/w peaking control 2. the peaking cur ve is controlled by scurve bit. 0 TW8823 ? tft flat panel controller techwell, inc. 124 rev a 11/20/2009 0x012d C miscellaneous control register i (misc1) bit function r/w description reset 7 reserved - reserved - 6 evcnt r/w 1 = even field counter in special mode 0 = normal operation. 0 5 reserved - reserved - 4 sdet r/w id detection sensitivity. a ?1? is reco mmended. 1 3 reserved - reserved - 2 bypass r/w debug use only 1 1-0 reserved - reserved - 0x012e C miscellaneous control register ii (misc2) bit function r/w description reset 7-6 hpm r/w horizontal pll acquisition time. 0 = slow 1 = auto1 2 = auto 3 = fast 2 5-4 acct r/w acc time constant 0 = no acc 1 = slow 2 = medium 3 = fas t 2 3-2 spm r/w burst pll control. 0 = slowest 1 = slow 2 = fast 3 = fastest 1 1-0 cbw r/w chroma low pass filter bandwidth contro l. 0 = low 1 = medium 2 = high 3 = extended 1 0x012f C miscellaneous control iii (misc3) bit function r/w description reset 7 nkill r/w 1 = enable noisy signal color killer fu nction in ntsc mode. 0 = disabled. 1 6 pkill r/w 1 = enable automatic noisy color killer function in pal mode. 0 = disabled. 1 5 skill r/w 1 = enable automatic noisy color killer function in secam mode. 0 = disabled. 1 4 cbal r/w 1 = special output mode 0 = normal output 0 3 fcs r/w 1 = force decoder output value determined by ccs. 0 = disabled. 0 2 lcs r/w 1 = enable pre-determined output value in dicated by ccs when video loss is detected. 0 = disabled. 0 1 ccs r/w when fcs is set high or video loss condit ion is detected when lcs is set high, one of two colors display can be selected. 1 = bluer. 0 = black. 0 0 bst r/w 1 = enable blue stretch. 0 = disabled. 0 TW8823 ? tft flat panel controller techwell, inc. 125 rev a 11/20/2009 0x0130 C macrovision detection bit function r/w description reset 7 sid_fail r secam id detection status, 1 = failed. - 6 pid_fail r pal id detection status, 1 = failed. - 5 fsc_fail r sub carrier frequency detection status , 1 = failed. - 4 slock_fail r sub carrier looking detection for st andard discrimination, 1 = failed. - 3 csbad r macrovision color strpe detection unstabl e, 1 = unstable. - 2 mcvsn r 1 = macrovision agc pulse detected. 0 = not detected. - 1 cstripe r 1 = macrovision color stripe protection burst detected. 0 = not detected. - 0 ctype2 r this bit is valid only when color stripe protection is detected, i.e. cstripe=1. 1 = type 2 color stripe protection 0 = type 3 color stripe protection - 0x0131 C cstatus iii bit function r/w description reset 7 vcr r 1 = vcr mode - 6 wkair r 1= weak signal 0 = normal - 5 wkair1 r weak signal indicator. - 4 vstd r 1 = standard signal 0 = non- standard signal - 3 nintl r 1 = non-interlaced signal 0 = interlace d signal - 2 wssdet r 1 = wss data detected. 0 = not detecte d. - 1 edsdet r 1 = eds data detected. 0 = not detecte d. - 0 ccdet r 1 = cc data detected. 0 = not detected. - 0x0132 C hfref bit function r/w description reset 7-0 reserved - reserved - 0x0133 C miscellaneous control register bit function r/w description reset 7-6 frm r/w free run mode. 0, 1 = auto mode 2 = 60 hz 3 = 50 hz 0 5-4 ynr r/w y hf noise reduction. 0 = none 1 = smallest 2 = s mall 3 = medium 0 3-2 clmd r/w clamping mode control. 0 = sync top 1 = auto 2 = p edestal 3 = n/a 1 1-0 psp r/w slice level for sync top mode. 0 = low 1 = medium 2 = h igh 3=highest 1 TW8823 ? tft flat panel controller techwell, inc. 126 rev a 11/20/2009 0x0134 C nsen/ssen/psen/wkth bit function r/w description reset 7-6 index r/w these two bits indicate which of the four lower 6-bit registers is currently being contr olled. the write sequence is a two steps process unless th e same register is written. a write of {id,000000} selects one of the four registers to be written. a subsequent write will actually write into the register. 0 5-0 nsen / ssen / psen / wkth r/w idx = 0 controls the ntsc id detection sensitiv ity (nsen). idx = 1 controls the secam id detection sensitivity (ssen). idx = 2 controls the pal id detection sensitivity ( psen). ids = 3 controls the weak signal detection sensitiv ity (wkth). 1a 0x0135 C clamp cntl2 bit function r/w description reset 7 ctest r/w clamping control for debug use. factory use only. 0 6 yclen r/w 1 = y channel clamp disabled 0 = enabled. 0 5 cclen r/w 1 = c channel clamp disabled 0 = enabled. 0 4 vclen r/w 1 = v channel clamp disabled 0 = enabled. 0 3 gtest r/w factory use only. 1 = test. 0 = normal operation. 0 2 vlpf r/w clamping filter control. factory use onl y. 0 1 ckly r/w clamping current control for y. factory use only. 0 0 cklc r/w clamping current control for c/v. factor y use only. 0 0x0138 C analog cntl bit function r/w description reset 7-1 reserved - reserved - 0 sy_c r/w yout control 0 = y 1 = y+c 0 TW8823 ? tft flat panel controller techwell, inc. 127 rev a 11/20/2009 lcdc C iirgb (input interface rgb) lcdc : adc/llpll 0x02c0 C llpll input control register bit function r/w description reset 7-6 inp_sel r/w sog input selection. 0 = sog0 1 = sog1 2 = na 3 = na 0 5 cs_inv r/w csync detection input polarity, active low needed. 0 = active high 1 = active low 0 4 cs_sel r/w pll input selection 0 = slicer or hs 1 = cs_pas 0 3 sog_sel r/w csync detection selection 0 = sog slicer 1 = hsync 0 2 hsy_pol r/w pll input polarity 0 = active low 1 = active high 0 1 reserved - reserved - 0 ck_sel r/w pll output clock selection 0 = select pll clock 1 = select oscillator clock 0 0x02c1 C llpll input detection register bit function r/w description reset 7 vs_pol r detected vsync polarity 0 = active low 1 = active high - 6 hs_pol r detected hsync polarity 0 = active low 1 = active high - 5 vs_det r vsync detection 0 = not detect 1 = detect - 4 hs_det r hsync detection 0 = not detect 1 = detect - 3 cs_det r composite sync detection 0 = not detect 1 = detect - 2-0 det_fmt r composite sync format detection 0 = 480i 1 = 576i 2 = 480p 3 = 576p 4 = 1080i 5 = 720p 6 = 1080p 7 = none of above - TW8823 ? tft flat panel controller techwell, inc. 128 rev a 11/20/2009 0x02c2 C llpll control register bit function r/w description reset 7-6 llc_post r/w pll post divider 0 = 1 1 = ? 2 = ? 3 = 1/8 0 5-4 llc_vco r/w vco range select (mhz) 0 = 5 ~ 27 1 = 10 ~ 54 2 = 20 ~ 108 3 = 40 ~ 216 0 3 reserved - reserved - 2-0 llc_ipmp r/w charge pump currents (ua) 0 = 1.5 1 = 2.5 2 = 5 3 = 10 4 = 20 5 = 40 6 = 80 7 = 160 0 0x02c3 C llpll divider high register bit function r/w description reset 7 ll_rstvco r/w rst_vco for llpll 0 6 ll_insel r/w pllin_sel for llpll 0 5-4 ll_icpsel r/w icp_sel[1:0] for llpll 0 3-0 llc_ackn[11: 8] r/w pll feedback divider. 3 0x02c4 C llpll divider low register bit function r/w description reset 7-0 llc_ackn[7:0] r/w pll feedback divider 5a 0x02c5 C llpll clock phase register bit function r/w description reset 7-5 reserved - reserved - 4-0 llc_pha r/w this 5bit value adjusts the samplin g phase in 32 steps across on pixel time. each step represents an 11.25 degree shift in sampling phase. 00 0x02c6 C llpll loop control register bit function r/w description reset 7 llc_acpl r/w pll loop control 0 = closed loop 1 = open loop 0 6-4 llc_apg r/w pll loop gain control 2 3 reserved - reserved - 2-0 llc_apz r/w pll filter control 0 TW8823 ? tft flat panel controller techwell, inc. 129 rev a 11/20/2009 0x02c7 C llpll vco control register bit function r/w description reset 7 ll_test r/w test_en for llpll 0 6 ll_bufe r/w buf_en for llpll 0 5 ll_vinen r/w vin_en for llpll 0 4 ll _5pf r/w lp_5pf for llpll 0 3-0 llc_acki[11 -8] r/w pll vco nominal frequency. reserved for int ernal use. 4 0x02c8 C llpll vco control register bit function r/w description reset 7-0 llc_acki[7-0] r/w pll_vco nominal frequency. re served for internal use. 00 0x02c9 C llpll pre coast register bit function r/w description reset 7-0 pre_coast r/w sets the number of hsync periods that coast is active before vsync edge. 06 0x02ca C llpll post coast register bit function r/w description reset 7-0 post_coast r/w sets the number of hsync periods that coast is active after vsync edge. 06 0x02cb C sog threshold register bit function r/w description reset 7 pusog r/w sog power down control 0 = power down 0 6 pupll r/w pll power down control 0 = power down 0 5 coast_en r/w pll coast control 1 = enable 1 4-0 sog_th[4:0] r/w sog slicer threshold this bits control the comparator threshold of the s og slicer at 10mv per every step. the setting value of 5??b00000 equals 330mv and the maximum setting value is 5?11111 which equals 10mv. 10 TW8823 ? tft flat panel controller techwell, inc. 130 rev a 11/20/2009 0x02cc C scaler sync selection register bit function r/w description reset 7-5 reserved - reserved - 4 vsy_sel r/w active vsync select 0 = composite sync separation output 1 = vsync input pin 0 3-2 hsy_sel r/w active hsync select 0 = hsync pin 1 = cs_pas 2 = sync separator output 3 = hso 0 1 vsy_polc r/w vsync polarity control 0 = active high 1 = active low 0 0 hsy_polc r/w hsync polarity control 0 = active high 1 = active low 0 0x02ce C rgb adc misc. register bit function r/w description reset 7 pinhssel r/w external pin hsync select 1 = pin hsync use 0 = internal signal use 0 6 pdr r/w adc power down for red channel 1 = power down 0 = normal operation 0 5 pdg r/w adc power down for green channel 1 = power down 0 = normal operation 0 4 pdb r/w adc power down for blue channel 1 = power down 0 = normal operation 0 3 dtv r/w adc input mode selection 1 = dtv 0 = rgb 0 2 clpen r/w enable clamp operation 1 = internal clamp use 0 = external clamp use 0 1 inrefv r/w adc reference voltage select 1 = internal reference disable 0 = internal reference enable 0 0 inrefi r/w adc bias reference current select 1 = bias current boost 0 = bias current normal 0 TW8823 ? tft flat panel controller techwell, inc. 131 rev a 11/20/2009 0x02cf C rgb adc misc2. register bit function r/w description reset 7-6 inp_sel_adc r/w adc data input pin select 3 = select input #3 2 = select input #2 1 = select input #1 0 = select input #0 0 5-0 save r/w pga/adc power save mode [5:3] = pga bias current control : bigger value mea ns smaller current setting [2:0] = adc bias current control : bigger value mea ns smaller current setting 09 0x02d0 C clamp gain control register bit function r/w description reset 7-3 reserved - reserved - 2 gainy[8] r/w y channel gain adjust bit[8] 0 1 gainc[8] r/w c channel gain adjust bit[8] 0 0 gainv[8] r/w v channel gain adjust bit[8] 0 TW8823 ? tft flat panel controller techwell, inc. 132 rev a 11/20/2009 0x02d1 C y channel gain adjust register bit function r/w description reset 7-0 gainy[7-0] r/w y channel gain adjust bit[7-0] f0 0x02d2 C c channel gain adjust register bit function r/w description reset 7-0 gainc[7-0] r/w c channel gain adjust bit[7-0] f0 0x02d3 C v channel gain adjust register bit function r/w description reset 7-0 gainv[7-0] r/w v channel gain adjust bit[7-0] f0 0x02d4 C clamp mode control register bit function r/w description reset 7 rgb_sel r/w rgb or ycv selection 0 = ycv mode 1 = rgb mod e 0 6 reserved - reserved - 5 cl_edge r/w clamp reference edge 0 4 clky r/w clamping current control 1 0 3 clkc r/w clamping current control 2 0 2 cl_y_en r/w green / y channel clamp 0 = enable, 1 = d isable 0 1 cl_c_en r/w blue / c channel clamp 0 = enable, 1 = d isable 0 0 cl_v_en r/w red / v channel clamp 0 = enable, 1 = d isable 0 0x02d5 C clamp start position register bit function r/w description reset 7-0 cl_st r/w this register sets programmable clamp ing start position. it is start count value that after the trailing ed ge of the hsync signal. 00 0x02d6 C clamp stop position register bit function r/w description reset 7-0 cl_ed r/w this register sets programmable clamp ing stop position. clamping duration set between start and stop positi on. 10 0x02d7 C clamp master location register bit function r/w description reset 7-0 cl_loc r/w this bit sets the rgb(ycv) clamp pos ition from the h sync edge. 70 TW8823 ? tft flat panel controller techwell, inc. 133 rev a 11/20/2009 0x02d8 C adc test register bit function r/w description reset 7 reserved - reserved - 6-4 llc_dbg_se l r/w debugging register for internal use 0 3 reserved - reserved - 2 rgb_adc_ test r/w internal test only 0 1 cl_test_y r/w programmable green / y select 0 = use default value (g:0x10, u/v:0x3c) 1 = programmable value 0 0 cl_test_uv r/w programmable blue and red / u and v select 0 = use default value (r/b:0x10, u/v:0x80) 1 = programmable value 0 0x02d9 C g clamp reference register bit function r/w description reset 7-0 cl_g_val r/w green channel clamping reference l evel in programmable mode. 10 0x02da C b clamp reference register bit function r/w description reset 7-0 cl_b_val r/w blue channel clamping reference l evel in programmable mode. 80 0x02db C r clamp reference register bit function r/w description reset 7-0 cl_r_val r/w red channel clamping reference lev el in programmable mode. 80 0x02dc C hsync width register bit function r/w description reset 7 edge_sel_l l r/w edge selection for llpll 0 6 reserved r/w reserved (set always to ?0?) 0 5-0 hswid r/w hsync widith. the unit of hwsid is on e clock cycle. 20 0x02dd C r channel adc offset register bit function r/w description reset 7-0 offsetr r/w r channel adc offset value. 00 0x02de C g channel adc offset register bit function r/w description reset 7-0 offsetg r/w g channel adc offset value. 00 0x02df C b channel adc offset register bit function r/w description reset 7-0 offsetb r/w b channel adc offset value. 00 TW8823 ? tft flat panel controller techwell, inc. 134 rev a 11/20/2009 lcdc C iidtv 1 (input interface dtv 1) 0x0300 C dtv1 input control bit function r/w description reset 7 ofdm r/w field detection method selection, applic able to dtv1 input only 0 = use the relationship between vsync pulse and h sync pulse 1 = use the vsync rising (or falling) edge locatio n inside or outside of the region defined by 0x0304 register 0 6 rvoddp r/w invert detected field signal, applicab le to dtv1 input only 0 5 slvsfld r/w use the rising or falling edge of vsy nc for field detection, applicable to dtv1 input on ly 0 = falling edge 1 = rising edge 0 4 deonly r/w de only selection, applicable to dtv1 only set this bit to ?1? if the input has de but no vsyn c and no hsync. 0 3 de_pol r/w invert de polarity, applicable to dtv1 only 0 = active high 1 = active low 0 2 hs_pol r/w invert hsync polarity, applicable to d tv1 only 0 = active high 1 = active low 0 1 vs_pol r/w invert vsync polarity, applicable to d tv1 only 0 = active high 1 = active low 0 0 - r/w reserved 0 0x0301 C dtv1 input control bit function r/w description reset 7 ? 6 - - reserved - 5 ext_ha r/w select explicit de ( data enable also called ha for horizontal active), applicable to dtv 1 only 0 = ha is asserted by each set of cropping registe rs (main path: 0x0410 ~ 0x0418, pip1: 0x2b0 ~ 0x2b5 , pip2: 0x2ca ~ 0x2cf 1 = ha is sourced by individual video source 1 4 selde r/w for dtv1 0 = dtvde is used as the data enable (de). 1 = dtvde is used as hsync input 0 3 reserved - reserved - 2 ? 0 dtvck_dela y r/w input clock dtvclk delay time selection. 0 = no delay time inserted. each incre ment increases the delay by 1 ns. 0 TW8823 ? tft flat panel controller techwell, inc. 135 rev a 11/20/2009 0x0302 C dtv1, rgb input control bit function r/w description reset 7 ? 6 - - reserved - 5 dtv1_vsdl_6 56 r/w itu656 even field vsync delay, applicable to dt v1 only 0 = no delay 1 = delay the assertion to the falling edge of ?h a? 0 4 dtv1_uva656 r/w enable alternative vsync generat ion for itu656 input, applicable to dtv1 only 0 = use ?f? bit in interlaced mode, and ?v? bit in progressive mode 1 = use ?v? bit in interlaced mode, and ?f? bit in progressive mode 0 3 dtv1_cr601 r/w cb/cr data order selection, applic able to dtv1 only set this bit to 1 in 8 bit 601 mode if the cr data arrives before cb data. 0 2 - 0 dtv1_prts r/w data bus routing selection for dtv1 for 24 bit ypbpr or 24 bit rgb dtv1d[23:16] dtv1d[15:8] dtv1d[7:0] 0: pr/b y/r pb/g 1: pr/b pb/g y/r 2: pb/g y/r pr/b 3: pb/g pr/b y/r 4: y/r pb/g pr/b 5: y/r pr/b pb/g for 16 bit ypb/pr: follow the table above with y a nd pb. example: if y data is connected to dtv1d[23:16] and pb/pr data is connected dtv1d[7:0], the bus routing selection should be set to ?101?. if explicit de, inde0x0301 bit [5], is set, the v ery first dtv1de is assumed to have pb data. on the other hand if ex plicit de is reset, index 0x0302 bit [3] is used to select the order of pb /pr. for 8 bit y/pb/pr: follow the table above with pr. example: if y/pb/pr data is connected to dtv1d[15:8 ], the bus routing selection can be set to ?011? or ?101?. use the table below for the correct data order. explicit de index-0x0302-bit-3 index 0x0301- bit-5 data order 1 x 0 pb-y-pr-y 1 x 1 pr-y-pb-y 0 0 0 pb-y-pr-y 0 0 1 pr-y-pb-y 0 1 0 y-pb-y-pr 0 1 1 y-pr-y-pb 4 TW8823 ? tft flat panel controller techwell, inc. 136 rev a 11/20/2009 0x0304 C dtv1 field detection region bit function r/w description reset 7 - 4 dtv1_ofd_d et_end r/w field detection horizontal ending locations, a pplicable to dtv1 only 5 3 -0 dtv1_ofd_d et_st r/w field detection horizontal starting locations, appl icable to dtv1 only 4 the decimal number in the ?start? column represents the starting clock count of a horizontal clock counter. the decimal number in the ?end? col umn represents the ending clock count. a field is distinguished by either the rising/falli ng edge of the vsync falls inside or outside of the region defined by the ?start? and ?end? pair. start end start end 0000 32 64 1000 512 1024 0001 64 128 1001 576 1152 0010 128 256 1010 640 1280 0011 192 384 1011 704 1408 0100 256 512 1100 768 1536 0101 320 640 1101 832 1664 0110 384 768 1110 896 1792 0111 448 896 1111 960 1920 0x0306 C dtv1 vsync delay bit function r/w description reset 7 - 0 dtv1_vsdel ay r/w input vsync delay, applicable to dtv1 only (on e input hsync per increment) 0 0x0307 C bit function r/w description reset 7-6 seqrgb_ltg r/w sequentiall rgb alternative line data based on rgb input order 3 = g->b->r 2 = r->g->b 1 = b->r->g 0 = g->b->r 0 5-4 seqrgb_or der r/w sequentiall rgb input order 3 = r->g->b 2 = b->r->g 1 = g->b->r 0 = r->g->b 0 3-2 segrgb_sel 8bit r/w sequentiall rgb input 8 bit selection out of [2 3:0] 3 = select 8 bit for [7:0] 2 = select 8 bit for [23:16] 1 = select 8 bit for [15:0] 0 = select 8 bit for [7:0] 0 1 seqrgb_pol r/w 0 = sequential rgb clock polarit y disable 1 = sequential rgb clock polarity inversion 0 0 seqrgb r/w 0 = sequential rgb mode disable 1 sequential rgb mode enable 0 TW8823 ? tft flat panel controller techwell, inc. 137 rev a 11/20/2009 0x0313 C test pattern generator control register bit function r/w description reset 7 tpg_en r/w 1: test pattern generator enable, 0: n ormal (dtv input) 6-4 tpg_cswap r/w color swap for test pattern gener ator 0: rgb (default) 1: gbr 2: brg 3: rbg 4: grb 5: bgr 6, 7: (same as 0) 3-0 tpg_pat r/w test pattern selection 0: 100% white vga sized border (1 dot thickness) w ith black inside 1: vga border (selection 0) plus h/v cross in the middle 2: gray scale 3: 100% blue 4: 100% blue (in rgb space) 5-f : 50% gray TW8823 ? tft flat panel controller techwell, inc. 138 rev a 11/20/2009 lcdc C iidtv 2 (input interface dtv 2) 0x0320 C dtv2 input control bit function r/w description reset 7 ofdm r/w field detection method selection, applic able to dtv2 input only 0 = use the relationship between vsync pulse and h sync pulse 1 = use the vsync rising (or falling) edge locatio n inside or outside of the region defined by 0x0324 register 0 6 rvoddp r/w invert detected field signal, applicab le to dtv2 input only 0 5 slvsfld r/w use the rising or falling edge of vsy nc for field detection, applicable to dtv2 input on ly 0 = falling edge 1 = rising edge 0 4 deonly r/w de only selection, applicable to dtv2 only set this bit to ?1? if the input has de but no vsyn c and no hsync. 0 3 de_pol r/w invert de polarity, applicable to dtv2 only 0 = active high 1 = active low 0 2 hs_pol r/w invert hsync polarity, applicable to d tv2 only 0 = active high 1 = active low 0 1 vs_pol r/w invert vsync polarity, applicable to d tv2 only 0 = active high 1 = active low 0 0 - r/w reserved 0 0x0321 C dtv2 input control bit function r/w description reset 7 ? 6 - - reserved - 5 ext_ha r/w select explicit de ( data enable also called ha for horizontal active), applicable to dtv 2 only 0 = ha is asserted by each set of cropping registe rs (main path: 0x0410 ~ 0x0418, pip1: 0x2b0 ~ 0x2b5 , pip2: 0x2ca ~ 0x2cf 1 = ha is sourced by individual video source 1 4 selde r/w for dtv2 0 = dtvde is used as the data enable (de). 1 = dtvde is used as hsync input 0 3 reserved - reserved - 2 ? 0 dtvck_dela y r/w input clock dtvclk delay time selection. 0 = no delay time inserted. each incre ment increases the delay by 1 ns. 0 TW8823 ? tft flat panel controller techwell, inc. 139 rev a 11/20/2009 0x0322 C dtv2, rgb input control bit function r/w description reset 7 ? 6 - - reserved - 5 dtv2_vsdl_6 56 r/w itu656 even field vsync delay, applicable to dt v2 only 0 = no delay 1 = delay the assertion to the falling edge of ?h a? 0 4 dtv2_uva656 r/w enable alternative vsync generat ion for itu656 input, applicable to dtv2 only 0 = use ?f? bit in interlaced mode, and ?v? bit in progressive mode 1 = use ?v? bit in interlaced mode, and ?f? bit in progressive mode 0 3 dtv2_cr601 r/w cb/cr data order selection, applic able to dtv2 only set this bit to 1 in 8 bit 601 mode if the cr data arrives before cb data. 0 2 - 0 dtv2_prts r/w data bus routing selection for dtv2 for 24 bit ypbpr or 24 bit rgb dtv2d[23:16] dtv2d[15:8] dtv2d[7:0] 0: pr/b y/r pb/g 1: pr/b pb/g y/r 2: pb/g y/r pr/b 3: pb/g pr/b y/r 4: y/r pb/g pr/b 5: y/r pr/b pb/g for 16 bit ypb/pr: follow the table above with y a nd pb. example: if y data is connected to dtv2d[23:16] and pb/pr data is connected dtv2d[7:0], the bus routing selection should be set to ?101?. if explicit de, inde0x0321 bit [5], is set, the v ery first dtv2de is assumed to have pb data. on the other hand if ex plicit de is reset, index 0x322 bit [3] is used to select the order of pb /pr. for 8 bit y/pb/pr: follow the table above with pr. example: if y/pb/pr data is connected to dtv2d[15:8 ], the bus routing selection can be set to ?011? or ?101?. use the table below for the correct data order. explicit de index-0x0322-bit-3 index 0x0321- bit-5 data order 1 x 0 pb-y-pr-y 1 x 1 pr-y-pb-y 0 0 0 pb-y-pr-y 0 0 1 pr-y-pb-y 0 1 0 y-pb-y-pr 0 1 1 y-pr-y-pb 4 TW8823 ? tft flat panel controller techwell, inc. 140 rev a 11/20/2009 0x0324 C dtv2 field detection region bit function r/w description reset 7 - 4 dtv2_ofd_d et_end r/w field detection horizontal ending locations, a pplicable to dtv2 only 5 3 -0 dtv2_ofd_d et_st r/w field detection horizontal starting locations, appl icable to dtv2 only 4 the decimal number in the ?start? column represents the starting clock count of a horizontal clock counter. the decimal number in the ?end? col umn represents the ending clock count. a field is distinguished by either the rising/falli ng edge of the vsync falls inside or outside of the region defined by the ?start? and ?end? pair. start end start end 0000 32 64 1000 512 1024 0001 64 128 1001 576 1152 0010 128 256 1010 640 1280 0011 192 384 1011 704 1408 0100 256 512 1100 768 1536 0101 320 640 1101 832 1664 0110 384 768 1110 896 1792 0111 448 896 1111 960 1920 0x0326 C dtv2 vsync delay bit function r/w description reset 7 - 0 dtv2_vsdel ay r/w input vsync delay, applicable to dtv2 only (on e input hsync per increment) 0 0x0327 C bit function r/w description reset 7-6 seqrgb_ltg r/w sequential rgb alternative line data based on rgb input order 3 = g->b->r 2 = r->g->b 1 = b->r->g 0 = g->b->r 0 5-4 seqrgb_or der r/w sequential rgb input order 3 = r->g->b 2 = b->r->g 1 = g->b->r 0 = r->g->b 0 3-2 segrgb_sel 8bit r/w sequential rgb input 8 bit selection out of [23 :0] 3 = select 8 bit for [7:0] 2 = select 8 bit for [23:16] 1 = select 8 bit for [15:0] 0 = select 8 bit for [7:0] 0 1 seqrgb_pol r/w 0 = sequential rgb clock polarit y disable 1 = sequential rgb clock polarity inversion 0 0 seqrgb r/w 0 = sequential rgb mode disable 1 sequential rgb mode enable 0 TW8823 ? tft flat panel controller techwell, inc. 141 rev a 11/20/2009 0x0333 C test pattern generator control register bit function r/w description reset 7 tpg_en r/w 1: test pattern generator enable, 0: n ormal (dtv2 input) 6-4 tpg_cswap r/w color swap for test pattern gener ator 0: rgb (default) 1: gbr 2: brg 3: rbg 4: grb 5: bgr 6, 7: (same as 0) 3-0 tpg_pat r/w test pattern selection 0: 100% white vga sized border (1 dot thickness) w ith black inside 1: vga border (selection 0) plus h/v cross in the middle 2: gray scale 3: 100% blue 4: 100% blue (in rgb space) 5-f : 50% gray TW8823 ? tft flat panel controller techwell, inc. 142 rev a 11/20/2009 lcdc C main path input cropping 0x0400 C main scaler control (soft reset, input se lection, etc) register bit function r/w description reset 7 sw_rst_sca ler r/w reset the scaler module 0 6 rvoddp99 r/w invert the internal decoder filed signal 0 5 lb_ce r/w line buffer chip enable 0 4 ? 2 reserved - reserved 0 1 ? 0 ip_sel r/w scaler input source selection; 0 = internal analog video decoder, 1 = analog rgb 2 = dtv1 3 = dtv2 0 0x0410 ~ 0x0411 main scaler active window horizont al start [10:0] registers 0x0410 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 - 0 ip_ha_st[10: 8] r/w main path input active window horizontal starti ng position - high 0 0x0411 low byte register bit function r/w description reset 7 - 0 ip_ha_st[7:0] r/w main path input active wind ow horizontal starting position ? low one pixel per increment 0 0x0412 ~ 0x0413 main scaler active window horizont al length [10:0] registers 0x0412 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 - 0 ip_ha_len[10 :8] r/w main path input active window horizontal length - high 2 0x0413 C low byte register bit function r/w description reset 7 - 0 ip_ha_len[7: 0] r/w main path input active window horizontal length ? low one pixel per increment d0h TW8823 ? tft flat panel controller techwell, inc. 143 rev a 11/20/2009 0x0414 ~ 0x0415 main scaler active window vertical start C odd field [10:0] 0x0414 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 - 0 ip_va_st_od d[10:8] r/w main path input active window odd field vertica l starting position - high 0 0x0415 C low byte register bit function r/w description reset 7 - 0 ip_va_st_od d[7:0] r/w main path input active window odd field vertica l starting position ? low one line per increment 13h 0x0416 C main scaler active window vertical start o ffset register C even field bit function r/w description reset 7 evn_offset _neg r/w positive or negative offset of even field from odd field. 0: positive ? even field vertical start later than odd field 1: negative ? even field vertical start earlier tha n odd field 0 6 - 0 ip_va_st_ev n_offset r/w offset value of the even field vertical startin g position from the odd field one line per increment 1 0x0417 ~ 0x0418 main scaler active window vertical length [10:0] registers 0x0417C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 - 0 ip_va_len[10 :8] r/w main path input active window vertical length - high 3 0x0418 C low byte register bit function r/w description reset 7 - 0 ip_va_len[7: 0] r/w main path input active window vertical length ? low one linel per increment 0 TW8823 ? tft flat panel controller techwell, inc. 144 rev a 11/20/2009 lcdc C scaling 0x0430 ~ 0x0432 horizontal up scaling factor [16:0 ] registers 0x0430 C high byte register bit function r/w description reset 7 ? 1 reserved - reserved 0 0 x_scale_up[ 16] r/w horizontal (x-direction) scale up factor - high 0 0x0431 C mid byte register bit function r/w description reset 7 ? 0 x_scale_up[ 15:8] r/w horizontal (x-direction) scale up factor - mid b4h 0x0432 C low byte register bit function r/w description reset 7 ? 0 x_scale_up[ 7:0] r/w horizontal (x-direction) scale up factor ? low horizontal scale up factor = 65536 * (input horizon tal active pixel number) / (flat panel horizontal active pixel number) example: vga 640x480 , panel resolution: 1024x76 8 65536 * 640 / 1024 = 40960 = 0a000h example: decoder 720x240, panel resolution: 1024x7 68 65536 * 720 / 1024 = 46080 = 0b400h 0 0x0433 ~ 0x0434 horizontal down scaling factor [8: 0] registers 0x0433 C high byte register bit function r/w description reset 7 ? 1 reserved - reserved 0 0 x_scale_do wn_[8] r/w horizontal (x-direction) scale down factor - high 0 0x0434 C low byte register bit function r/w description reset 7 ? 0 x_scale_do wn_lo r/w horizontal (x-direction) scale down factor - low horizontal scale down factor = 128 * (input horizon tal active pixel number) / (flat panel horizontal active pixel number) example: decoder 720x240, panel resolution: 640x48 0 128 * 720 / 640 = 144 = 090h 80h TW8823 ? tft flat panel controller techwell, inc. 145 rev a 11/20/2009 0x0435 ~ 0x0437 vertical scaling factor [17:0] reg isters 0x0435 C high byte register bit function r/w description reset 7 ? 2 reserved - reserved 0 1 ? 0 y_scale_up/ down [17:16] r/w vertical (y-direction) scale up/down factor ? high 0 0x0436 C mid byte register bit function r/w description reset 7 ? 0 y_scale_up/ down [15:8] r/w vertical (y-direction) scale up/down factor ? mid 50h 0x0437 C low byte register bit function r/w description reset 7 ? 0 y_scale_up/ down [7:0] r/w vertical (y-direction) scale up/down factor ? low the vertical scale factor can be derived in two way s: 1. use active line number vertical scale factor = 65536 * (input vertical a ctive line number) / (flat panel vertical active line number) 2. use total line number vertical scale factor = 65536 * (input vertical t otal line number) / (flat panel vertical period line number) example: vga 640x480 , panel resolution: 1024x76 8 65536 * 480 / 768 = 40960 = 0a000h example: decoder total vertical lines in one field 262.5, panel vertical periods: 802 65536 * 262.5 / 802 = 21450 = 053cah 0 0x0438 C horizontal up scaling offset [7:0] regist er bit function r/w description reset 7 - 0 x_offset r/w horizontal (x-direction) scale up offset this offset is used to adjust the initial value for the x-direction scale up operation. 0 0x0439 C vertical scaling offset [7:0] register (o dd field) bit function r/w description reset 7- 0 y_odd_offs et r/w vertical (y-direction) scale up offset for odd fiel d this offset is used to adjust the initial value for the y-direction scale up operation. 0 0x043a C vertical scaling offset [7:0] register (e ven field) bit function r/w description reset 7 - 0 y_evn_offs et r/w vertical (y-direction) scale up offset for even fie ld this offset is used to adjust the initial value for the y-direction scale up operation. 80h 0x043b C misc scaling control register bit function r/w description reset 7 reserved - reserved 0 6 lndb r/w 1 = line doubling 0 = normal vertical scaling 0 5 pxdb r/w 1 = pixel doubling 0 = n ormal horizontal scaling 0 4 zoombp r/w set zoom by-pass. when this bit is set , the horizontal and vertical scale up factors has no effects. 0 3 - 0 reserved - reserved 0 TW8823 ? tft flat panel controller techwell, inc. 146 rev a 11/20/2009 0x043c ~ 0x043d panorama width registers 0x043c C high byte register bit function r/w description reset 7 pano_ena r/w enable panorama scaling operation 1: enable 0: disable 0 6-2 reserved - reserved 0 1- 0 pana_width _hi r/w panorama horizontal width - high 0 0x043d C low byte register bit function r/w description reset 7 - 0 pana_width _lo r/w panorama horizontal width - low 0 0x043e C horizontal up scaling factor for panorama register bit function r/w description reset 7 - 0 x_scale_up _pan r/w horizontal scale at the side of display in panorama scaling mode. 0 0x043f C horizontal down scaling filter bit function r/w description reset 7 dnsfil_man r/w 1 = down scaler pre-filter manual mode 0 = auto mode 0 6 - 2 reserved - reserved 0 1 - 0 dnsfil_mod e r/w down scaler pre-filter manual selection 0 = no filter ? 3 = strongest 0 TW8823 ? tft flat panel controller techwell, inc. 147 rev a 11/20/2009 lcdc C panel display control 0x0470 C display control register bit function r/w description reset 7 rgb2bsft- up r/w rgb output 2 bit shift up 0 6 dual_selh r/w 0 = panel data output selection low er 24 of 48 bits 1 = panel data output selection upper 24 of 48 bit s 0 5 fpdata_zer o r/w fp digital data all zero 0 = normal 1 = da ta all zero 0 4 - 2 reserved - reserved 0 1 data_0 r/w force scaler data output to all 0?s 0 0 data_blu r/w force scaler data output blue 0 0x0471 C panel output signal control register bit function r/w description reset 7 swap_fprg b r/w swapping red and blue data bus 0 = no swapping 1 = data bus swapping red and bl ue 0 6 reserved - reserved 0 5 demode r/w de mode selection 1= fpvs a nd fphs are forced to inactive state. 0 4 op6b r/w fp data outputs shift down 2 bits. when set, fpr0, fpr1, fpg0, fpg1, fpb0, fpb1 bus signals are shifted down by 2 bits. 0 3 trifp r/w tri-state all the output signals to fla t panel. 0 2 - 0 reserved - reserved 0 0x0472 ~ 0x0473 panel output hsync period [11:0] re gisters 0x0472 C high byte register bit function r/w description reset 7 - 4 reserved - reserved 0 3 - 0 fphs_perio d [7:0] r/w fphs period - high byte 5 0x0473 C low byte register bit function r/w description reset 7 - 0 fphs_perio d [7:0] r/w fphs period - low byte one pixel or panel clock per increment 3ah 0x0474 C panel output hsync pulse width [7:0] regis ter bit function r/w description reset 7 - 0 fphs_activ e_pw r/w fphs active pulse width this register is usually filled in with the minimum fphs pulse width requirement from the flat panel specification 10h TW8823 ? tft flat panel controller techwell, inc. 148 rev a 11/20/2009 0x0475 C panel output hsync back porch [7:0] regist er bit function r/w description reset 7 - 0 fp_h_back_ porch r/w flat panel horizontal back porch width one pixel or panel clock per increment this register is usually filled in with the minimum horizontal back porch requirement from the flat panel specification. when the reg_0489[6] is set to ?0?, this register h as no effect on horizontal back porch; an internal circuitry calculates the horizontal back p orch to center the active region; reading this register returns the calculated value. if the valu e returned is 0xff, the actual value can be larger than 0xff. refer to reg_04c0 ~ reg_04c3 for reading the calculated values 1bh 0x0476 ~ 0x0477 panel output horizontal active widt h [10:0] registers 0x0476 C high byte register bit function r/w description reset 7 - 3 reserved - reserved 0 2 - 0 fpde_active [10:8] r/w fpde horizontal active length -high 4 0x0477 C low byte register bit function r/w description reset 7 - 0 fpde_active [7:0] r/w fpde horizontal active length -low 0 0x0478 ~ 0x479 panel output vsync period [10:0] reg ister 0x0478 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 ? 0 fpvs_perio d [10:8] r/w fpvs period - high 3 0x0479 C low byte register bit function r/w description reset 7 ? 0 fpvs_perio d [7:0] r/w fpvs period - low one fphs period per increment 26h 0x047a C panel output vsync pulse width [7:0] regi ster bit function r/w description reset 7 ? 0 fpvs_active _pw r/w fpvs active pulse width one fphs period per increment this register is usually filled in with the minimum fpvs pulse width requirement from the flat panel specification. 06 0x047b C panel output vsync back porch [7:0] regis ter bit function r/w description reset 7 ? 0 fp_v_back_ porch r/w flat panel vertical back porch width one fphs period per increment 1fh TW8823 ? tft flat panel controller techwell, inc. 149 rev a 11/20/2009 0x047c ~ 0x047d panel output vertical active length [10:0] register 0x047c C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 7 ? 0 fp_v_active [10:8] r/w flat panel vertical active length - high 3 0x047d C low byte register bit function r/w description reset 7 ? 0 fp_v_active [7:0] r/w flat panel vertical active length - low 0 0x0480 ~ 0x0481 horizontal non display width [9:0] registers 0x0480 C high byte register bit function r/w description reset 7 - 2 reserved - reserved - 1 - 0 h_non_disp lay [9:8] r/w horizontal non-display pixel number applied to both left and right sides - high 0 0x0481 C low byte register bit function r/w description reset 7 - 0 h_non_disp lay [7:0] r/w horizontal non-display pixel number applied to both left and right sides - low 0 0x0482 ~ 0x0483 horizontal non display width ii [9: 0] independent left/right selection registers 0x0482 C high byte register bit function r/w description reset 7 thnd2_en r/w 1 = non-display left/right independent control enab le. use 0x0480[1:0] and 0x048 only for left side and use 0x0482[1:0] and 0x0483 for right side 0 = use 0x0480[1:0] and 0x0481 for both left and r ight 0 6 - 2 reserved - reserved 0 1 - 0 ri_non_disp lay [9:8] r/w non display width for right side - high 0 0x0483 C low byte register bit function r/w description reset 7 - 0 ri_non_disp lay [7:0] r/w non display width for right side - high 0 0x0484 C top / bottom display black out register bit function r/w description reset 7 - 6 reserved - reserved 0 5 - 0 blktb r/w number of lines to be black out fr om top and the bottom of the display. 0 TW8823 ? tft flat panel controller techwell, inc. 150 rev a 11/20/2009 0x0485 C bottom display black out register bit function r/w description reset 7 blktb2_en r/w enable independent top and bottom b lack out line numbers. the top black out line numb er is set by reg_0484[5:0] and the bottom black out line is set by reg_0485[5:0] 0 6 reserved - reserved 0 5 - 0 blktb2 r/w blcok bottom 0 0x0486 C fpen delay adjustment register bit function r/w description reset 7 int_de_no_de lay - disable the delay specified by 0x0486[3:0] 0 6 - 4 reserved - reserved 0 3 - 0 int_de_dela y r/w delay tuning for flat panel output de 0 0x0487 C fphs delay adjustment register bit function r/w description reset 7-4 reserved - reserved 0 3-0 fphs_ output_ delay r/w adjust the panel fphs output delay. a non zero value effectively moves the fphs closer to the fpde. 0 0x0488 C fpvs delay adjustment register bit function r/w description reset 7 - 4 reserved - reserved 0 3 - 0 delay_fpvs r/w adjust fpvs position. a higher value moves the fpv s closer to the first active display line (the first active fpde). 8 0x0489 C panel adjustment selection register bit function r/w description reset 7 utvb r/w disable the alignment of the first input active li ne to the first display output line when reg_048b[7] is set to ?1? 0: always aligned 1: the display up/down movement can be adjusted by changing reg_048c, the fpvs pulse width, or back porch 0 6 uthb r/w 0 = panel horizontal back porch value is from auto calculation 1 = panel horizontal back porch value follows the reg_8075 0 5 dist_hadj r/w enable distributed fphs period minor adjustment effective when usereg (reg_807e_[0]) is ?0? and re g_807e[6] is ?1? 0 4 ena_hadj r/w enable fphs period minor adjustment no effect if usereg, reg_807e_[0] is ?1? 0 3 - 2 reserved - reserved 0 1 autoc r/w enable auto calculation of initial counter valu e. when this bit is ?1?, an internal circuitry calculates the initial value of horizontal pixel co unter, which in turn generates fphs. the calculation is based on either the internal generat ed fphs period or the programmed fphs period, determined by reg_0489[0]. if this bit is ?0?, the initial value is taken fro m reg_0490[7:0] ~ reg_0493[7:0] 0 0 usereg r/w fphs period selection: 1: the contents programmed in index reg_0472 and in dex reg_0473 0: internal circuit generated value 0 TW8823 ? tft flat panel controller techwell, inc. 151 rev a 11/20/2009 0x048a C panel adjustment selection register bit function r/w description reset 7 ? 6 reserved - reserved 0 5 early_st r/w early start. start to output data e arlier in non auto calculation mode. 0 4 - r/w reserved 0 3 afrun r/w enable auto free run. if the input vsy nc is lost, the free run mode is automatically invo ked. (the reg 0x0b09 bit 0 must set to 1 to detect the v sync loss) 0 2 frerun r/w force into free run mode. 0 1 reserved - reserved 0 0 tcon_de_c on r/w enable internal de to tcon module always genera ted 1: enable 0: disable 0 0x048b C internal panel timing adjustment register bit function r/w description reset 7 line_vscl r/w use fpvs period, reg_0478 reg_0479 to generate vertical scale factor. the result is r ead back from vertical scale factor registers, reg_0435 reg_0436, and reg_0437. 1: enable 0: disable 0 6 frm_alin r/w frame alignment 1: vsync 0: non vsync 0 5 fld_alin r/w non vsync frame alignment occurs at odd filed only or both fields 1: odd field 0: both fields 0 4 alow_qer r/w sampling quantization error allowanc e 1: no 0: yes 0 3 - 0 thrsh_vch g r/w threshold of one frame clock count to perform n ew frame alignment 4 0x048c C internal panel timing adjustment register bit function r/w description reset 7 - 0 linegonum r/w this register is used when the line_vscl (reg_048b[7]) is ?1? and the utvb (reg_04 89[7]) is ?0? to move the fpvs position. a larger value m oves the fpvs earlier. 24h 0x048d C panel adjustment selection register bit function r/w description reset 7 - 6 disp_sngfl d r/w display single field on flat panel. 0,1 = function disabled 2 = display o dd field 3 = display even field 0 5 rvg_ac r/w when set the field signal is reversed in the auto calculation circuitry. 0 4 oldtime r/w when the auto calculation bit (reg_80 7e[1]) is turned off and this bit is set, the vsync generation falls back to the old way. 0 3 - 0 reserved - reserved 0 1 - 0 evndly r/w even field vertical back porch adj ustment 0 = 0 1 = +1 2 = +2 3 = -1 0 TW8823 ? tft flat panel controller techwell, inc. 152 rev a 11/20/2009 0x0490 ~ 0x0491 pixel counter initialization value [12:0] registers (odd field) 0x0490 C high byte register bit function r/w description reset 7 - 5 reserved - reserved 0 4 - 0 ini_cnt_odd [12:8] r/w pixel counter initialization value --high 0 0x0491 C low byte register bit function r/w description reset 7 - 0 ini_cnt_odd [7:0] r/w pixel counter initialization value ? low this register comes into effect when the ?autoc? r eg_0489[1] is set to ?0?. it provides the initial value of horizontal pixel counter for the o dd field. c0h 0x0492 ~ 0x0493 pixel counter initialization value [12:0] registers (even field) 0x0492 C high byte register bit function r/w description reset 7 - 5 reserved - reserved 0 4 - 0 ini_cnt_evn [12:8] r/w pixel counter initialization value --high 0 0x0493 C low byte register bit function r/w description reset 7 - 0 ini_cnt_evn [7:0] r/w pixel counter initialization value ? low this register comes into effect when the ?autoc? r eg_0489[1] is set to ?0?. it provides the initial value of horizontal pixel counter for the e ven field. c0h 0x0494 C line buffer read start location [7:0] regi ster bit function r/w description reset 7 - 0 tgt_pos r/w this register comes into effect when the ?autoc?, reg_0489[1] is set to ?1?. it is used to set the internal line buffer fifo read start time. a s maller value makes the read start later. use only even number as percentage of one fphs period. c0h TW8823 ? tft flat panel controller techwell, inc. 153 rev a 11/20/2009 0x04c0 ~ 0x04c3 internal counter read out registers bit function r/w description reset 7 - 0 counter_re ad_byte_3, _2,_1, _0 r these four index addresses provide real time data r ead out of some internal counters. the index of these counters is set by reg_04c6[7:4] . index 0x04c0 0x04c1 0x04c2 0x04c3 0 - lvpcnt_odd[23:16] lvpcnt_odd[15:8] lvpcnt_odd[7:0] 1 - lvpcnt_evn[23:16] lvpcnt_evn[15:8] lvpcnt_evn[7:0] 2 livcnt_evn[15:8] livcnt_evn[7:0] livcnt_odd[11:8] l ivcnt_odd[7:0] 3 hcnt_oddi[15:8] hcnt_oddi[7:0] lhcnt_oddi[11:8] lhc nt_oddi[7:0] 4 lbovfc[10:8] lbovfc[7:0] lhpcnt[13:8] lhpcnt[7:0] 5 fpgo_evn_h[12:8 ] fpgo_evn_h [7:0] fpgo_odd_h[12:8 ] fpgo_odd_h[7:0 ] 6 fpgo_evn_v[10:8 ] fpgo_evn_v [7:0] fpgo_odd_v[10:8 ] fpgo_odd_v [7:0] 7 tvbm[10:8] tvbm[7:0] thbm[10:8] thbm[7:0] 8 fpvpos_evn[11:8 ] fpvpos_evn [7:0] fpvpos_odd[11:8 ] fpvpos_odd[7:0 ] - 0x04c4 C simulation initialization register bit function r/w description reset 7 - 4 pccinia_ index r/w index for simulation initialization of internal aut o calculation counters. 0: vpcnt[23:0] pixel counter for 1 vs ync period 1: lvpcnt_odd[23:0] pixel counter for 1 odd field vsync period 2: lvpcnt_evn[23:0] pixel counter for 1 even fiel d vsync period 3: ivcnt[11:0] line counter for 1 v sync period 4: livcnt_odd[11:0] line counter for 1 odd field vsync period 5: livcnt_evn[11:0] line counter for 1 even fie ld vsync period 0 3 frc_2f r/w for internal use only 0 2 frc_1f r/w for internal use only 0 1 - 0 pccinia_ sub_indx r/w sub index for the above counters, providing byte wi de data read/write from/to 0x0c1. 0 = bits [7:0] of the counter pointed by the inde x 1 = bits [15:8] of the counter pointed by the ind ex 2 = bits [23:16] of the counter pointed by the in dex 0 0x04c5 C simulation initialization data port regist er bit function r/w description reset 7 - 0 pccinid r/w data port for the counters listed in 0x04c4 0 0x04c6 C data read selection register bit function r/w description reset 7-4 rd_indx r/w index for selecting which data to read from 0x04c0 ~ 0x04c3 0 3-0 - r/w reserved 0 TW8823 ? tft flat panel controller techwell, inc. 154 rev a 11/20/2009 lcdc C image adjustment 0x0500 C main image adjustment register bit function r/w description reset 7-6 reserved - reserved - 5-0 hue r/w hue adjustment for main path. these bit s control the color hue. the range is +45 degrees t o ?45 degrees in 1.4 degree increments. 0 degrees is the default (xx10 0000) 20 0x0501 C main image adjustment register bit function r/w description reset 7-0 contrast_r r/w red contrast adjustment for main path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0502 C main image adjustment register bit function r/w description reset 7-0 contrast_g r/w green contrast adjustment for ma in path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0503 C main image adjustment register bit function r/w description reset 7-0 contrast_b r/w blue contrast adjustment for mai n path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0504 C main image adjustment register bit function r/w description reset 7-0 contrast_y r/w y contrast adjustment for main p ath 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0505 C main image adjustment register bit function r/w description reset 7-0 contrast_cb r/w cb contrast adjustment for main path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0506 C main image adjustment register bit function r/w description reset 7-0 contrast_cr r/w cr contrast adjustment for main path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 TW8823 ? tft flat panel controller techwell, inc. 155 rev a 11/20/2009 0x0507 C main image adjustment register bit function r/w description reset 7-0 brightness _r r/w red brightness adjustment for main path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x0508 C main image adjustment register bit function r/w description reset 7-0 brightness _g r/w green brightness adjustment for main path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x0509 C main image adjustment register bit function r/w description reset 7-0 brightness _b r/w blue brightness adjustment for main path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x050a C main image adjustment register bit function r/w description reset 7-0 brightness _y r/w y brightness adjustment for main path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x050b C main image adjustment register bit function r/w description reset 7-4 h_sharp_ cor r/w coring function for sharpness control of main p ath. 3 3-0 h_sharpness r/w sharpness adjustment for main path 0 0x050c C main image adjustment register bit function r/w description reset 7 h_sharp_fr eq r/w main path sharpness frequency select 0 = low freq 1 = high freq 0 6 reserved - reserved - 5-4 dynr r/w main path ynr 0 3 reserved - reserved - 2-0 hflt r/w main path hflt. 0 TW8823 ? tft flat panel controller techwell, inc. 156 rev a 11/20/2009 0x0510 C pip1 image adjustment register bit function r/w description reset 7-6 reserved - reserved - 5-0 hue r/w hue adjustment for pip1 path. these bits control th e color hue. the range is +45 degrees to ?45 degrees in 1.4 degree increments. 0 degrees is the default (xx10 0000) 20 0x0511 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_r r/w red contrast adjustment for pip1 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0512 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_g r/w green contrast adjustment for pi p1 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0513 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_b r/w blue contrast adjustment for pip 1 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0514 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_y r/w y contrast adjustment for pip1 p ath 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0515 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_cb r/w cb contrast adjustment for pip1 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0516 C pip1 image adjustment register bit function r/w description reset 7-0 contrast_cr r/w cr contrast adjustment for pip1 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 TW8823 ? tft flat panel controller techwell, inc. 157 rev a 11/20/2009 0x0517 C pip1 image adjustment register bit function r/w description reset 7-0 brightness _r r/w red brightness adjustment for pip1 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x0518 C pip1 image adjustment register bit function r/w description reset 7-0 brightness _g r/w green brightness adjustment for pip1 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x0519 C pip1 image adjustment register bit function r/w description reset 7-0 brightness _b r/w blue brightness adjustment for pip1 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x051a C pip1 image adjustment register bit function r/w description reset 7-0 brightness _y r/w y brightness adjustment for pip1 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x051b C pip1 image adjustment register bit function r/w description reset 7-4 h_sharp_ cor r/w coring function for sharpness control of pip1 p ath. 3 3-0 h_sharpness r/w sharpness adjustment for pip1 path 0 0x051c C pip1 image adjustment register bit function r/w description reset 7 h_sharp_fr eq r/w pip1 path sharpness frequency select 0 = low freq 1 = high freq 0 6 reserved - reserved - 5-4 dynr r/w pip1 path ynr 0 3 reserved - reserved - 2-0 hflt r/w pip1 path hflt. 0 0x0520 C pip2 image adjustment register bit function r/w description reset 7-6 reserved - reserved - 5-0 hue r/w hue adjustment for pip2 path. these bits control th e color hue. the range is +45 degrees to ?45 degrees in 1.4 degree increments. 0 degrees is the default (xx10 0000) 20 TW8823 ? tft flat panel controller techwell, inc. 158 rev a 11/20/2009 0x0521 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_r r/w red contrast adjustment for pip2 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0522 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_g r/w green contrast adjustment for pi p2 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0523 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_b r/w blue contrast adjustment for pip 2 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0524 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_y r/w y contrast adjustment for pip2 p ath 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0525 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_cb r/w cb contrast adjustment for pip2 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0526 C pip2 image adjustment register bit function r/w description reset 7-0 contrast_cr r/w cr contrast adjustment for pip2 path 80h+ = higher contrast 80h = neutral 80h- = lower contrast 80 0x0527 C pip2 image adjustment register bit function r/w description reset 7-0 brightness _r r/w red brightness adjustment for pip2 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 TW8823 ? tft flat panel controller techwell, inc. 159 rev a 11/20/2009 0x0528 C pip2 image adjustment register bit function r/w description reset 7-0 brightness _g r/w green brightness adjustment for pip2 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x0529 C pip2 image adjustment register bit function r/w description reset 7-0 brightness _b r/w blue brightness adjustment for pip2 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x052a C image adjustment register bit function r/w description reset 7-0 brightness _y r/w y brightness adjustment for pip2 path 80h+ = higher brightness 80h = neutral 80h- = lower brightness 80 0x052b C pip2 image adjustment register bit function r/w description reset 7-4 h_sharp_ cor r/w coring function for sharpness control of pip2 p ath. 3 3-0 h_sharpness r/w sharpness adjustment for pip2 path 0 0x052c C pip2 image adjustment register bit function r/w description reset 7 h_sharp_fr eq r/w pip2 path sharpness frequency select 0 = low freq 1 = high freq 0 6 reserved - reserved - 5-4 dynr r/w pip2 path ynr 0 3 reserved - reserved - 2-0 hflt r/w pip2 path hflt. 0 0x0530 C image adjustment register bit function r/w description reset 7 t_bw r/w test bw. should be 0 for normal operatio n 0 6 reserved - reserved - 5 pedlvl r/w black level selection. 0 = 0 1 = 16d 0 4 whtlvl r/w white level selection. 0 = 235d 1 = 255d 1 3-1 reserved - reserved - 0 bw_en r/w 0 = bw disable 1 = b w stretch enable 0 TW8823 ? tft flat panel controller techwell, inc. 160 rev a 11/20/2009 0x0531 C image adjustment register bit function r/w description reset 7-0 bw_line_st_l o r/w black/white stretch line start for detection wi ndow, lower 8 bits ( total 10 bits). 08 0x0532 C image adjustment register bit function r/w description reset 7-0 bw_line_end _lo r/w black/white stretch line end for detection wind ow, lower 8 bits ( total 10 bits). f6 0x0533 C image adjustment register bit function r/w description reset 7-4 reserved - reserved. 0 3-2 bw_line_en d_hi r/w black/white stretch line end for detection window, upper 2 bits. 2 1-0 bw_line_st_ hi r/w black/white stretch line startfor detection window, upper 2 bits. 0 0x0534 C image adjustment register bit function r/w description reset 7-0 bw_h_delay r/w bwhdly, black/white stretc horiz ontal distance from start/end pixel of hactive. 10 0x0535 C image adjustment register bit function r/w description reset 7-6 reserved - reserved - 5-0 bw_h_filte r_gain r/w y min/max horizontal filter gain. 0d 0x0536 C image adjustment register bit function r/w description reset 7-0 bw_black_ tilt r/w tilt point for black stretch. 67 0x0537 C image adjustment register bit function r/w description reset 7-0 bw_white_ tilt r/w tilt point for white stretch. 94 TW8823 ? tft flat panel controller techwell, inc. 161 rev a 11/20/2009 0x0538 C image adjustment register bit function r/w description reset 7-0 bw_black_ limit r/w black stretch limit 2a 0x0539 C image adjustment register bit function r/w description reset 7-0 bw_white_ limit r/w white stretch limit d0 0x053a C image adjustment register bit function r/w description reset 7 reserved - reserved - 6-0 bw_gain r/w black/white stretch field recursive filter gain. 02 0x0550 C image adjustment register bit function r/w description reset 7-0 ce_center0 r/w color enhancement center color p hase for color 1. the range for center color phase is ? 180 ~ + 180, 2 degree per step. color enhancement center is 2?s complement form, de fault degree of center 0 is 122 3d 0x0551 C image adjustment register bit function r/w description reset 7-0 ce_center1 r/w color enhancement center color p hase for color 2. the range for center color phase is ? 180 ~ + 180, 2 degree per step. color enhancement center is 2?s complement form, de fault degree of center 1 is ?122 c3 0x0552 C image adjustment register bit function r/w description reset 7-0 ce_center2 r/w color enhancement center color p hase for color31. the range for center color phase is ? 180 ~ + 180, 2 degree per step. color enhancement center is 2?s complement form, de fault degree of center 2 is ?8 fc 0x0553 C image adjustment register bit function r/w description reset 7 ce_en r/w 1= color enhancement enable 0 = disable 0 6-5 ce_spread0 r/w color enhancement gain spread range for color 1 0 = no enhance 1 = -8 ~ +8 of center color phase 2 = -16 ~ +16 of center color phase 3 = -32 ~ + 32 of center color phase 0 4-0 ce_gain0 r/w color enhancement gain for color 1 . the minimum gain value is 00000 and maximum is 11111 from 0 to 0.484 with 31 step of 1/64. 0 TW8823 ? tft flat panel controller techwell, inc. 162 rev a 11/20/2009 0x0554 C image adjustment register bit function r/w description reset 7 reserved - reserved - 6-5 ce_spread1 r/w color enhancement gain spread ra nge for color 2 0 = no enhance 1 = -8 ~ +8 of center color phase 2 = -16 ~ +16 of center color phase 3 = -32 ~ + 32 of center color phase 0 4-0 ce_gain1 r/w color enhancement gain for color 2 . the minimum gain value is 00000 and maximum is 11111 from 0 to 0.484 with 31 step of 1/64. 0 0x0555 C image adjustment register bit function r/w description reset 7 reserved - reserved - 6-5 ce_spread2 r/w color enhancement gain spread range for color 3 0 = no enhance 1 = -8 ~ +8 of center color phase 2 = -16 ~ +16 of center color phase 3 = -32 ~ + 32 of center color phase 0 4-0 ce_gain2 r/w color enhancement gain for color 3 . the minimum gain value is 00000 and maximum is 11111 from 0 to 0.484 with 31 step of 1/64. 0 0x0570 C test pattern generator register bit function r/w description reset 7 tpg_en r/w test pattern generator enable, 0: norm al (dtv input) 0 6-4 tpg_cswap r/w color swap for test pattern gener ator 0: rgb (default) 1: gbr 2: brg 3: rbg 4: grb 5: bgr 6, 7: (same as 0) 0 3-0 pat_sel r/w pattern selection. 0: hue map 1: hue map (fine) 2: gray horizontal 17 steps 3: gray vertical 17 steps 4: gray h/v 17x17 steps 5: white rectangle 6: vertical 1-dot stripe 7: horizontal 1-dot stripe 8: black/white checker board 9: rgb checker board a: gray horizontal 17 steps + horizontal black stri pes b: mitsubishi wqvga test pattern c: flat 100% blue d: ramp e, f: flat 50% gray 0 TW8823 ? tft flat panel controller techwell, inc. 163 rev a 11/20/2009 TW8823 ? tft flat panel controller techwell, inc. 164 rev a 11/20/2009 lcdc C pip1 control 0x0600 C pip control register bit function r/w description reset 7-2 reserved r/w - 1-0 pipgw_xst[9 :8] r/w horizontal input cropping start[9:8]. these bits in dicate the start point of the cropping window of the pip data which is going to be written into m emory. 0 0x0601 C pip control register bit function r/w description reset 7-0 pipgw_xst[7 :0] r/w horizontal input cropping start[7:0]. these bit s indicate the start point of the cropping window of the pip data which is going to be written into m emory. 00 0x0602 C pip control register bit function r/w description reset 7-3 reserved r/w - 2-0 pipgw_widt h[10:8] r/w horizontal input cropping window width[10:8]. these bits indicate the width of the cropping window of the pip data which is going to be written into memory. 2 0x0603 C pip control register bit function r/w description reset 7-0 pipgw_widt h[7:0] r/w horizontal input cropping window width[7:0]. th ese bits indicate the width of the cropping window of the pip data which is going to be written into memory. d0 0x0604 C pip control register bit function r/w description reset 7-1 reserved r/w - 0 pipgw_yst[8] r/w vertical input cropping start[8] . 0 0x0605 C pip control register bit function r/w description reset 7-0 pipgw_yst[7:0] r/w vertical input cropping start[7:0]. these bits indicate the start point of the cropping window of the pip data which is going to be written into memo ry. 02 0x0606 C pip control register bit function r/w description reset 7-3 reserved r/w vertical input cropping start[8]. 0 2-0 pipgw_heig ht[10:8] r/w vertical input cropping window height[10:8]. 0 TW8823 ? tft flat panel controller techwell, inc. 165 rev a 11/20/2009 0x0607 C pip control register bit function r/w description reset 7-0 pipgw_heig ht[7:0] r/w vertical input cropping window height[7:0]. the se bits indicate the height of the cropping window of the pip data which is going to be written into memory. e0 0x0608 C pip control register bit function r/w description reset 7 ppfil_man r/w 1 = down scaler pre-filter manual selection enable . 0 = auto selection (default) 0 6 ckinv r/w 1 = pip input clock inverse 0 = normal. 0 5-4 ppfil_sel r/w down scaler pre-filter manual selection. 0 = no filter 1 = weak filter 2 = strong filter 3 = medium filter 0 3-2 pipefdoff r/w even field offset for the croppin g window. 0 1-0 pipofdoff r/w odd field offset for the cropping window. 0 0x0609 C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pipdnsxfac[ 11:8] r/w pip horizontal down scaling ratio [11:8]. 1 0x060a C pip control register bit function r/w description reset 7-0 pipdnsxfac[ 7:0] r/w pip horizontal down scaling ratio [7:0]. 100h f or no down scaling. 00 0x060b C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pipdnsyfac[ 11:8] r/w pip vertical down scaling ratio [11:8]. 1 0x060c C pip control register bit function r/w description reset 7-0 pipdnsyfac[ 7:0] r/w pip vertical down scaling ratio [7:0]. 100h for no down scaling 00 0x060d C pip control register bit function r/w description reset 7 pdof_en1 r/w 1 = pip1 down scaler offset enable ( interlace input), 0 = offset disabled (progressive input) 0 6-0 pip_dn_off1 r/w pip1 down scaler offset (40h = half line offset) 00 TW8823 ? tft flat panel controller techwell, inc. 166 rev a 11/20/2009 0x060e C pip control register bit function r/w description reset 7-0 pip_wr_ base[23:16] r/w pip window write buffer base address. it defines st art address of pip memory area. 00 0x060f C pip control register bit function r/w description reset 7-0 pip_wr_ base[15:8] r/w pip window write buffer base address. it defines st art address of pip memory area. 00 0x0610 C pip control register bit function r/w description reset 7-0 pip_wr_ base[7:0] r/w pip window write buffer base address. it defines st art address of pip memory area. 00 0x0611 C pip control register bit function r/w description reset 7-3 reserved r/w - 2-0 pip_wr_wid th[10:8] r/w pip window write width[10:8]. these bits indicate t he width of the pip window written into the memory. maximum width is 400h. 2 0x0612 C pip control register bit function r/w description reset 7-0 pip_wr_wid th[7:0] r/w pip window write width[7:0]. these bits indicat e the width of the pip window written into the memory. d0 0x0613 C pip control register bit function r/w description reset 7-2 reserved r/w - 1-0 height[9:8] r/w pip window write height[9:8]. 0 0x0614 C pip control register bit function r/w description reset 7-0 pip_wr_heig ht[7:0] r/w pip window write height[7:0]. these bits indica te the height of the pip window written into the memory. e0 TW8823 ? tft flat panel controller techwell, inc. 167 rev a 11/20/2009 0x0615 C pip control register bit function r/w description reset 7 pipwren r/w 1 = pip window write enable. when di sabled read-out image will freeze. 0 6 wcph r/w write data color phase control. 1 5 mute_c r/w pip1 mute color selection 1 = blue 0 = black, only active when 0x2bd[0] = 1 0 4-1 reserved r/w - 0 prcph r/w read data color phase control 0 0x0616 C pip control register bit function r/w description reset 7 prden r/w 1 = pip window read enable 0 6 frm_md r/w 1 = pip frame based buffer control (drop/duplicate frame) 0 = field based (default) 0 5 pipen r/w pip mode enable. 0 4 sngl_fd r/w 1 = pip blending single field mode 0 = normal 0 3 rdfdpol r/w pip read buffer field polarity 0 2 pxdb r/w 1 = pixel doubling when up scaling 0 = normal. 0 1 lndb r/w 1 = line doubling when up scaling 0 = normal 0 0 mute_en r/w 1 = pip1 image mute 0 = nor mal. mute color defined by 0x2bc[5] 0 0x0617 C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pupsxfac[11 :8] r/w pip horizontal up scaling ratio [11:8]. 8 0x0618 C pip control register bit function r/w description reset 7-0 pupsxfac[7: 0] r/w pip horizontal up scaling ratio [7:0]. 800h for no up scaling. 00 0x0619 C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pupsyfac[11 :8] r/w pip vertical up scaling ratio [11:8]. 8 0x061a C pip control register bit function r/w description reset 7-0 pupsyfac[7: 0] r/w pip vertical up scaling ratio [7:0]. 800h for no up scaling. 00 TW8823 ? tft flat panel controller techwell, inc. 168 rev a 11/20/2009 0x061b C pip control register bit function r/w description reset 7-0 upsfdoff r/w pip1 vertical upscale field offset. only work with interlaced input. 80 0x061c C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pipwbasex [11:8] r/w pip window position base x start[11:8]. these bits indicate the origin of the pip window. 0 0x061d C pip control register bit function r/w description reset 7-0 pipwbasex[7 :0] r/w pip window position base x start[7:0]. these bits i ndicate the origin of the pip window. 00 0x061e C pip control register bit function r/w description reset 7-3 reserved r/w - 2-0 pipwbasey [10:8] r/w pip window position base y start[10:8]. these bits indicate the origin of the pip window. 0 0x061f C pip control register bit function r/w description reset 7-0 pipwbasey[7 :0] r/w pip window position base y start[7:0]. these bits i ndicate the origin of the pip window. 00 0x0620 C pip control register bit function r/w description reset 7-4 pipwyoff r/w pip window position base y start o ffset. these bits indicate the base position of the pip window. 3 3-0 pipwxoff r/w pip window position base x start o ffset. these bits indicate the base position of the pip window. c 0x0621 C pip control register bit function r/w description reset 7-4 reserved r/w - 3-0 pipwwidth[1 1:8] r/w pip window width[11:8]. these bits indicate the dis play width of the pip window. 2 TW8823 ? tft flat panel controller techwell, inc. 169 rev a 11/20/2009 0x0622 C pip control register bit function r/w description reset 7-0 pipwwidth[7 :0] r/w pip window width[7:0]. these bits indicate the disp lay width of the pip window. d0 0x0623 C pip control register bit function r/w description reset 7-3 reserved r/w - 2-0 pipwheight[ 10:8] r/w pip window height[10:8]. these bits indicate the di splay height of the pip window. 0 0x0624 C pip control register bit function r/w description reset 7-0 pipwheight[ 7:0] r/w pip window height[7:0]. these bits indicate the dis play height of the pip window. e0 0x0625 C pip control register bit function r/w description reset 7-0 pip_h_pos_a dj r/w pip horizontal position offset adjustment f4 0x0626 C pip control register bit function r/w description reset 7-0 pip_v_pos_a dj r/w pip vertical position offset adjustment fc TW8823 ? tft flat panel controller techwell, inc. 170 rev a 11/20/2009 lcdc C pip2 control 0x0630 C pip2 control register bit function r/w description reset 7-2 reserved r/w - 1-0 pip2gw_xst[ 9:8] r/w horizontal input cropping start[9:8]. these bits in dicate the start point of the cropping window of the pip2 data which is going to be written into memory. 0 0x0631 C pip2 control register bit function r/w description reset 7-0 pip2gw_xst[ 7:0] r/w horizontal input cropping start[7:0]. these bit s indicate the start point of the cropping window of the pip2 data which is going to be written into memory. 00 0x0632 C pip2 control register bit function r/w description reset 7-3 reserved r/w - 2-0 pip2gw_wid th[10:8] r/w horizontal input cropping window width[10:8]. these bits indicate the width of the cropping window of the pip2 data which is going to be writte n into memory. 2 0x0633 C pip2 control register bit function r/w description reset 7-0 pip2gw_wid th[7:0] r/w horizontal input cropping window width[7:0]. th ese bits indicate the width of the cropping window of the pip2 data which is going to be writte n into memory. d0 0x0634 C pip2 control register bit function r/w description reset 7-1 reserved r/w - 0 pip2gw_yst[8] r/w vertical input cropping start[8 ]. 0 0x0635 C pip2 control register bit function r/w description reset 7-0 pip2gw_yst[7:0 ] r/w vertical input cropping start[7:0]. these bits indicate the start point of the cropping window of the pip2 data which is going to be written into mem ory. 02 0x0636 C pip2 control register bit function r/w description reset 7-3 reserved r/w vertical input cropping start[8]. 0 2-0 pip2gw_hei ght[10:8] r/w vertical input cropping window height[10:8]. 0 TW8823 ? tft flat panel controller techwell, inc. 171 rev a 11/20/2009 0x0637 C pip2 control register bit function r/w description reset 7-0 pip2gw_hei ght[7:0] r/w vertical input cropping window height[7:0]. the se bits indicate the height of the cropping window of the pip2 data which is going to be writte n into memory. e0 0x0638 C pip2 control register bit function r/w description reset 7 ppfil_man r/w 1 = down scaler pre-filter manual selection enable . 0 = auto selection (default) 0 6 ckinv r/w 1 = pip2 input clock inverse 0 = normal. 0 5-4 ppfil_sel r/w down scaler pre-filter manual selection. 0 = no filter 1 = weak filter 2 = strong filter 3 = medium filter 0 3-2 pip2efdoff r/w even field offset for the croppi ng window. 0 1-0 pip2ofdoff r/w odd field offset for the croppin g window. 0 0x0639 C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pip2dnsxfa c[11:8] r/w pip2 horizontal down scaling ratio [11:8]. 1 0x063a C pip2 control register bit function r/w description reset 7-0 pip2dnsxfa c[7:0] r/w pip2 horizontal down scaling ratio [7:0]. 100h for no down scaling. 00 0x063b C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pip2dnsyfa c[11:8] r/w pip2 vertical down scaling ratio [11:8]. 1 0x063c C pip2 control register bit function r/w description reset 7-0 pip2dnsyfa c[7:0] r/w pip2 vertical down scaling ratio [7:0]. 100h for no down scaling 00 0x063d C pip2 control register bit function r/w description reset 7 pdof_en2 r/w 1 = pip2 down scaler offset enable ( interlace input), 0 = offset disabled (progressive input) 0 6-0 pip2_dn_off 2 r/w pip2 down scaler offset (40h = half line offset) 00 TW8823 ? tft flat panel controller techwell, inc. 172 rev a 11/20/2009 0x063e C pip2 control register bit function r/w description reset 7-0 pip2_wr_ base[23:16] r/w pip2 window write buffer base address. it defines s tart address of pip2 memory area. 00 0x063f C pip2 control register bit function r/w description reset 7-0 pip2_wr_ base[15:8] r/w pip2 window write buffer base address. it defines s tart address of pip2 memory area. 00 0x0640 C pip2 control register bit function r/w description reset 7-0 pip2_wr_ base[7:0] r/w pip2 window write buffer base address. it defines s tart address of pip2 memory area. 00 0x0641 C pip2 control register bit function r/w description reset 7-3 reserved r/w - 2-0 pip2_wr_wi dth[10:8] r/w pip2 window write width[10:8]. these bits indicate the width of the pip2 window written into the memory. maximum width is 400h. 2 0x0642 C pip2 control register bit function r/w description reset 7-0 pip2_wr_wi dth[7:0] r/w pip2 window write width[7:0]. these bits indica te the width of the pip2 window written into the memory. d0 0x0643 C pip2 control register bit function r/w description reset 7-2 reserved r/w - 1-0 height[9:8] r/w pip2 window write height[9:8]. 0 0x0644 C pip2 control register bit function r/w description reset 7-0 pip2_wr_hei ght[7:0] r/w pip2 window write height[7:0]. these bits indic ate the height of the pip2 window written into the memory. e0 TW8823 ? tft flat panel controller techwell, inc. 173 rev a 11/20/2009 0x0645 C pip2 control register bit function r/w description reset 7 pip2wren r/w 1 = pip2 window write enable. when disabled read-out image will freeze. 0 6 wcph r/w write data color phase control. 1 5 mute_c r/w pip2 mute color selection 1 = blue 0 = black, only active when 0x2bd[0] = 1 0 4-1 reserved r/w - 0 prcph r/w read data color phase control 0 0x0646 C pip2 control register bit function r/w description reset 7 prden r/w 1 = pip2 window read enable 0 6 frm_md r/w 1 = pip2 frame based buffer control (drop/duplicat e frame) 0 = field based (default) 0 5 pip2en r/w pip2 mode enable. 0 4 sngl_fd r/w 1 = pip2 blending single field mode 0 = normal 0 3 rdfdpol r/w pip2 read buffer field polarity 0 2 pxdb r/w 1 = pixel doubling when up scaling 0 = normal. 0 1 lndb r/w 1 = line doubling when up scaling 0 = normal 0 0 mute_en r/w 1 = pip2 image mute 0 = nor mal. mute color defined by 0x2bc[5] 0 0x0647 C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pupsxfac[11 :8] r/w pip2 horizontal up scaling ratio [11:8]. 8 0x0648 C pip2 control register bit function r/w description reset 7-0 pupsxfac[7: 0] r/w pip2 horizontal up scaling ratio [7:0]. 800h for no up scaling. 00 0x0649 C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pupsyfac[11 :8] r/w pip2 vertical up scaling ratio [11:8]. 8 0x064a C pip2 control register bit function r/w description reset 7-0 pupsyfac[7: 0] r/w pip2 vertical up scaling ratio [7:0]. 800h for no u p scaling. 00 TW8823 ? tft flat panel controller techwell, inc. 174 rev a 11/20/2009 0x064b C pip2 control register bit function r/w description reset 7-0 upsfdoff r/w pip2 vertical upscale field offset. only work with interlaced input. 80 0x064c C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pip2wbasex [11:8] r/w pip2 window position base x start[11:8]. these bits indicate the origin of the pip2 window. 0 0x064d C pip2 control register bit function r/w description reset 7-0 pip2wbasex[ 7:0] r/w pip2 window position base x start[7:0]. these bits indicate the origin of the pip2 window. 00 0x064e C pip2 control register bit function r/w description reset 7-3 reserved r/w - 2-0 pip2wbasey [10:8] r/w pip2 window position base y start[10:8]. these bits indicate the origin of the pip2 window. 0 0x064f C pip2 control register bit function r/w description reset 7-0 pip2wbasey[ 7:0] r/w pip2 window position base y start[7:0]. these bits indicate the origin of the pip2 window. 00 0x0650 C pip2 control register bit function r/w description reset 7-4 pip2wyoff r/w pip2 window position base y start offset. these bits indicate the base position of t he pip2 window. 3 3-0 pip2wxoff r/w pip2 window position base x start offset. these bits indicate the base position of t he pip2 window. c 0x0651 C pip2 control register bit function r/w description reset 7-4 reserved r/w - 3-0 pip2wwidth[ 11:8] r/w pip2 window width[11:8]. these bits indicate the di splay width of the pip2 window. 2 TW8823 ? tft flat panel controller techwell, inc. 175 rev a 11/20/2009 0x0652 C pip2 control register bit function r/w description reset 7-0 pip2wwidth[ 7:0] r/w pip2 window width[7:0]. these bits indicate the dis play width of the pip2 window. d0 0x0653 C pip2 control register bit function r/w description reset 7-3 reserved r/w - 2-0 pip2wheigh t[10:8] r/w pip2 window height[10:8]. these bits indicate the d isplay height of the pip2 window. 0 0x0654 C pip2 control register bit function r/w description reset 7-0 pip2wheigh t[7:0] r/w pip2 window height[7:0]. these bits indicate the di splay height of the pip2 window. e0 0x0655 C pip2 control register bit function r/w description reset 7-0 pip2_h_pos_ adj r/w pip2 horizontal position offset adjustment f4 0x0656 C pip2 control register bit function r/w description reset 7-0 pip2_v_pos_ adj r/w pip2 vertical position offset adjustment fc TW8823 ? tft flat panel controller techwell, inc. 176 rev a 11/20/2009 lcdc C pip1/pip2 common control 0x0660 C pip1/2 control register bit function r/w description reset 7 pip2_mrr r/w 1: pip2 image mirroring, 0: normal 0 6-4 pip_border h[2:0] r/w pip1/pip2 vertical border width [2:0] (0 line ? 7 l ines) 0 3 pip1_mrr r/w 1: pip1 image mirroring, 0: normal 0 2-0 pip_border w[2:0] r/w pip1/pip2 horizontal border width (0 dot ? 7 dots) 0 0x0661 C pip1/2 control register bit function r/w description reset 7-0 pip_frmcol or1 r/w pip1/pip2 standard window frame color 1c 0x0662 C pip1/2 control register bit function r/w description reset 7-0 pip_frmcol or1 r/w pip1/pip2 standard window frame color 1c 0x0663 C reserved bit function r/w description reset 7 pip_rstn r/w pip local software reset (auto return to 0) 0 6-0 reserved r/w reserved 00 TW8823 ? tft flat panel controller techwell, inc. 177 rev a 11/20/2009 lcdc C dv, pip1/pip2 comm on control 0x0670 C dual view control register (only for inte rnal and special customer) bit function r/w description reset 7 reserved r/w 0 6 dv_reverse r/w 1: left/right image swap, 0: norma l 0 5 reserved r/w 0 4 dv_checker r/w 1: checker dv pattern, 0: stripe b arrier dv pattern 0 3-2 lr_same r/w 0x: l/r show different image, 01: l /r both show pip image, 10: l/r both show main imag e 00 1 reserved r/w 0 0 dv_en r/w 1: dual view enable, 0: disable 0 0x0671 C pip1/2 control register bit function r/w description reset 7 dtvde1 r/w 1 = dtv1 input de is ignored for both pip1 and pip 2 0 = de is used 1 6 dtvde2 r/w 1= dtv2 input de is ignored for both pip1 and pip2 0 = de is used 1 5 dvlden3 r/w 1: ignore decoder cken 0 4 reserved - reserved - 3-2 pip_inmx_ sel r/w pip1 input selection. 0 = decoder 1 = analog rgb/yuv 2 = dtv1 3 = dtv2 0 1-0 pip2_inmx_ sel r/w pip2 input selection. 0 = decoder 1 = analog rgb/yuv 2 = dtv1 3 = dtv2 0 0x0672 C pip1/2, blending control register bit function r/w description reset 7-6 pipmx_ipsel r/w pip mixing mode. 0 = pip2 over pip1 alpha blended with main (pip1 is the main image and pip2 is the sub window) 1 = pip1 over pip2 alpha blended with main (pip2 is the main image and pip1 is the sub windiw) 2 = pip2 over main alpha blended with pip1 (main is the main image and pip2 is the sub window) 3 = pip1 over main alpha blended with pip2 (main is the main image and pip1 is the sub window) 3 5 pipmx1_en r/w 1 = primary path sub window enable (default) 0 = primary path sub window disable this apply for normal panel or either one side of i mage of dual view panel image. this register has priority over 0x0616[5], 0x0646[5] reg isters 1 4 pipmx2_en r/w 1 = secondary path sub window enable (default), 0 = secondary path sub window disable. this bit ha s priority than alpha blending selection in bit 3. this apply for either one side of dual view panel i mage. 1 3 alpmx_en r/w 1 = secondary path alpha blending enable 0 = secondary path alpha blending disable (default ) this apply for either one side of dual view panel i mage. 0 2 2nd_pip r/w 1 = pip2 border on 0 1 pip2_wr_pw dn r/w 1 = pip2 write power down (image will freeze) 0 = normal 0 0 pip_wr_pwd n r/w 1 = pip1 write power down (image will freeze) 0 = normal 0 TW8823 ? tft flat panel controller techwell, inc. 178 rev a 11/20/2009 0x0673 C dual view control register (only for inte rnal and special customer) bit function r/w description reset 7-3 reserved r/w - 2 v_toggle r/w 1: inversion polarity alternate every field, 0: inv ersion polarity stay the same for every field 0 1 h_phase r/w 1: 2-dot inversion start with same polarity for fir st 2 pixels, 0: 2-dot inversion polarity changes between first and second pixel (default) 0 0 tpo_mode r/w 1: 2-dot + line inversion operation for tpo pan el, 0: normal 0 TW8823 ? tft flat panel controller techwell, inc. 179 rev a 11/20/2009 lcdc C pip alpha blending control 0x0680 C pip alpha blending register bit function r/w description reset 7 blend_en r/w 1 = pip alpha blending enable 0 = disable 0 6 mode565 r/w 1 = 565 mode (4:4:4 color space) for pip 0 = 888 mode (4:2:2 color space) default 0 5 key_rev r/w 1 = pip alpha blending key detection reverse 0 = normal 0 4-0 alpha1 r/w alpha1 of pip alpha blending (main/sub mixing ratio ), 2 = full pip ? 0 = full main 10 0x0681 C pip alpha blending register bit function r/w description reset 7 keydisp r/w 1 = pip overlay key color position display for test. 0 6-5 reserved - reserved - 4-0 alpha2 r/w alpha2 of pip alpha blending (main dimming) 2 = full main ? 0 = black 10 0x0682 C pip alpha blending register bit function r/w description reset 7-0 rkey r/w red key color level for pip alpha blending 00 0x0683 C pip alpha blending register bit function r/w description reset 7-0 gkey r/w green key color level for pip alpha blending 00 0x0684 C pip alpha blending register bit function r/w description reset 7-0 bkey r/w blue key color level for pip alpha blending 00 0x0685 C pip alpha blending register bit function r/w description reset 7-0 rrange r/w key color range for red 00 0x0686 C pip alpha blending register bit function r/w description reset 7-0 grange r/w key color range for green 00 0x0687 C pip alpha blending register bit function r/w description reset 7-0 brange r/w key color range for blue 00 TW8823 ? tft flat panel controller techwell, inc. 180 rev a 11/20/2009 lcdc C osd 0x0700 C 0sg control register bit function r/w description reset 7 ? 6 osgmod e r/w osg write operation mode 00: mcu/dma write operation 01: block transfer (no bit expansion, 0x0700[1:0] s hould be ?00?) 10: block fill (no bit expansion, 0x0700[1:0] shoul d be ?00?) 11: block transfer with source linear addressing 00 5 ? 4 msksel r/w bitblt function select 00: selective overwrite 01: mask from source word 10: mask from bitblt mask register 11: no bitblt function (unprocessed source pixel i s written to destination location) 00 3 color_c on r/w enable color conversion when this bit is set and the source pixel value mat ches the value specified by the color conversion source color register (0x0740 ~ 0x0747), the pixel is converted to the corresponding color conversion target color registe r value (0x0748 ~ 0x074f) 0 2 bpp r/w pixel unit selection 0: 2 bytes per pixel (16 bit) 1: 1 byte per pixel ( 8bit) 0 1 - 0 bexpm r/w bit expansion selection. when expanding to 8 bit (1 byte per pixel), the ?8 bit expansion table? is used. when expanding to 16 bit (2 bytes per pixel), the ? 16 bit expansion table? is used. to invoke the special 8 to 16 bit expansion, the 0x 0703[4] needs to be set to ?1? 00: no bit expansion 01: expand 1 bit to 8/16 bit 10: expand 2 bit to 8/16 bit 11: expand 4 bit to 8/16 bit, or special 8 to16 bit 000 TW8823 ? tft flat panel controller techwell, inc. 181 rev a 11/20/2009 0x0701 C osg control register bit function r/w description reset 7 osg_stu s osg operation status: a ?1? indicates the operation is busy and a ?0? means the operation is done. 0 6 fifo_stu s when osdmode=00 (mcu/dma write), this bit indicates the fifo full status. a ?1? means fifo is full and cannot accept new data. if the osdmode is not ?00?, this bit is always ?0? but the fifo is not accessible. 0 5 - 2 reserved 0 1 mcuwd r/w mcu data write done. this bit is used for mcu write operation (osdmode=2?b00 and 0x0703[6]=0) only. normally, if the amount of data is enough to cover the transfer destination region, defined by transfer horizontal length (0x0768, 0x0769) and tra nsfer vertical length (ox76a,0x076b), the osg busy status bit , 0x0701[7], will be de-ass erted after the transfer is done. there is no need to set this bit. if the amount of data is not enough, one can write this bit to ?1? after the mcu has written all the data. once this bit is set, additional data wi ll be padded until the transfer destination region is fully filled. the osg busy status will be de-asserted afterwards. 0 0 op_star t r/w write ?1? to start osg operation; and ?0? to stop t he operation. operation sequence for block fill and block transfe r: after setting all the other registers, write a ?1? to start operation, then read back bit [7] to check the status. if the status returns ?0?, write a ?0? to finish the operation. if without wr iting a ?0?, the subsequent write ?1? has no effect. operation sequence for mc/dma write: similar to blo ck fill and block transfer except that after writing a ?1? to this bit the operation does not start until 64 bytes data is written to the data port for mcu/dma write (0x0702). if more data are required, continue to write to the data port with additional 64 bytes chunks. when al l writes are done and the bit [7] status returns ?0?, write a ?0? to end the operation. 0 TW8823 ? tft flat panel controller techwell, inc. 182 rev a 11/20/2009 0x0702 C data port for mcu write register bit function r/w description reset 7 ? 0 - w data port - 0x0703 C osd/osg control register bit function r/w description reset 7 - r/w reserved 0 6 osd_hw r/w enable osd hardware handshake with internal mcu. s et this bit to 1, when the spi dma is used to source the write data. 1: enable 0: disable 0 5 - 4 - r/w reserved - 4 sp8to16 r/w special osg 8 bit expansion to 16 bit operation. . the special operation mode requires setting this bi t to ?1?, the 0x0700[2:0] = 3?b011, and the 0x0703[3:1] a valid rgb format code. in the special 8 to 16 bit expansion, the entry 0 i n the 16 bit expansion table is always used as the expanded source pixel which is blended with the target pixel. the (alpha) blending value comes from the content of the original 8 bit source. the lower the alpha value, the less the expanded source pixel is shown. in this special 8 to 16 bit expansion mode, the color conversion, bitblt, and the selective over write fu nctions are disabled. 0 3 - 1 osg16fo rm -- format selection for destination 16 bit type during the special osg 8 bit to 16 bit operation 001: rgb565 (r 5, g 6, b 5) data[15:0] = {r[4:0],g [5:4],g[3:0],b[4:0]} 010: rgb4444 (alpha 4, r 4, g 4, b 4) data[15:0] = {a[3:0],r[3:0],g[3:0],b[3:0]} 011: rgb1555 (blink 1, r 5, g 5, b 5) data[15:0] = {bl, r[4:0],g[4:0],b[4:0]} 0 0 osdsrst r/w soft reset for osd section 0 0x0704 ~ 0x0705 osd rlc registers 0x0704 C osd rlc register bit function r/w description reset 7 - 5 reserved - reserved - 4 rlc_pkt e r/w rlc packet enable 0: disable 1: enable 0 3 - 2 reserved - reserved - 1 rlc_res et r/w rlc reset 0: normal 1: reset 0 0 rlc_ena r/w rlc function enable 0: disable 1: enable 0 0x0705 C osd rlc register bit function r/w description reset 7 ? 4 rlc_dcn t r/w rlc data count bit 0 3 - 0 rlc_cnt t r/w rlc counter count bit 0 0x0706 C osd/osg control register bit function r/w description reset 7 osdtest r/w osd test 0 6 - 1 - r/w reserved - 0 osdpdn r/w power down osd module 0 TW8823 ? tft flat panel controller techwell, inc. 183 rev a 11/20/2009 0x070b C bitblt logic register bit function r/w description reset 7 ? 0 bbltmem r/w bitblt logic operation register the content of this register specifies the bit wise logic operation of bitblt mask register, destination pixel, and source pixel. for each bit wise index ?i?, the three bit combinat ion of bitblt_mask_register[i], destination_pixel[i], and source_pixel[i] uniquely points to one bit location in bitblt logic register. this bitblt logic register (bblr) bit co ntent specifies the resulting bit wise logic operation. the following truth table is used in establishing t he default content of bblr. this default value provides the logic operation of 1) if mask bit is ? 1?, the outcome follows the destination pixel, 2) if mask bit is ?0?, the outcome follows the sour ce pixel bitblt_mask_register[i] destination_pixel[i] source_pixel[i] result bblr bit (bblr content) position 1 1 1 1 7 1 1 0 1 6 1 0 1 0 5 1 0 0 0 4 0 1 1 1 3 0 1 0 0 2 0 0 1 1 1 0 0 0 0 0 1100 1010 0x070c ~ 0x070d bitblt mask register 0x070c C high byte register bit function r/w description reset 7 ? 0 - r/w bitblt mask, high byte; not used for 8 bit color 0 0x070d C low byte register bit function r/w description reset 7 ? 0 - r/w bitblt mask, low byte 0 0x070e ~ 0x070f block fill color 0x070e C high byte register bit function r/w description reset 7 ? 0 - r/w fill color register for block fill oper ation, high byte for 16 bit color; not used for 8 b it color 0 0x070f C low byte register bit function r/w description reset 7 ? 0 - r/w fill color register for block fill oper ation, low byte for 16 bit color 0 TW8823 ? tft flat panel controller techwell, inc. 184 rev a 11/20/2009 0x0710 ~ 0x071f 8 bit color expansion table 0x0710 C entry 0 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 8 bit color 0 0x0711 C entry 1 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 8 bit color 0 0x071f C entry 15 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 8 bit color 0 0x0720 ~ 0x073f 16 bit color expansion table 0x0720 C entry 0 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color high byte 0 0x0721 C entry 0 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color low byte 0 0x0722 C entry 1 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color high byte 0 0x0723 C entry 1 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color low byte 0 0x073e C entry 15 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color high byte 0 0x073f C entry 15 register bit function r/w description reset 7 ? 0 - r/w data for bit expansion to 16 bit color low byte 0 TW8823 ? tft flat panel controller techwell, inc. 185 rev a 11/20/2009 0x0740 ~ 0x0747 color conversion source color 0x0740 C entry 0 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, high byte for 16 bit color; not used for 8 bit color 0 0x0741 C entry 0 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, low byte for 16 bit color source pixel that matches this entry is converted t o the corresponding target color 0 0x0742 C entry 1 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, high byte for 16 bit color; not used for 8 bit color 0 0x0743 C entry 1 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, low byte for 16 bit color source pixel that matches this entry is converted t o the corresponding target color 0 0x0744 C entry 2 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, high byte for 16 bit color; not used for 8 bit color 0 0x0745 C entry 2 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, low byte for 16 bit color source pixel that matches this entry is converted t o the corresponding target color 0 0x0746 C entry 3 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, high byte for 16 bit color; not used for 8 bit color 0 0x0747 C entry 3 register bit function r/w description reset 7 ? 0 - r/w source color comparison register, low byte for 16 bit color source pixel that matches this entry is converted t o the corresponding target color 0 TW8823 ? tft flat panel controller techwell, inc. 186 rev a 11/20/2009 0x0748 ~ 0x074f color conversion target color 0x0748 C entry 0 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source c olor entry 0, high byte for 16 bit color; not used for 8 bit color 0 0x0749 C entry 0 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source color entry 0, low byte for 16 bit colo r 0 0x074a C entry 1 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source c olor entry 1, high byte for 16 bit color; not used for 8 bit color 0 0x074b C entry 1 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source color entry 1, low byte for 16 bit colo r 0 0x074c C entry 2 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source c olor entry 2, high byte for 16 bit color; not used for 8 bit color 0 0x074d C entry 2 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source color entry 2, low byte for 16 bit colo r 0 0x074e C entry 3 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source c olor entry 3, high byte for 16 bit color; not used for 8 bit color 0 0x074f C entry 3 register bit function r/w description reset 7 ? 0 - r/w target color register corresponding to the source color entry 3, low byte for 16 bit colo r 0 TW8823 ? tft flat panel controller techwell, inc. 187 rev a 11/20/2009 0x0750 ~ 0x0757 selective overwrite 0x0750 C entry 0 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 0, high byte fo r 16 bit color; not used for 8 bit color selective overwrite function is invoked when the ms ksel (0x0700_bit[5:4]) is set to ?00?. source pixel after source color conversion is compa red against this selective overwrite register. if there is a comparison match, the pixe l is further processed by bitblt logic. if the bblr (0x070b) has the default reset value, t hen the comparison match will result in the destination keeping the original content; while the mismatch will result in the destination replaced by the color-conversion-processed source p ixel. 0 0x0751 C entry 0 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 0, low byte for 16 bit color 0 0x0752 C entry 1 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 1, high byte for 16 bit color; not used for 8 bit col or 0 0x0753 C entry 1 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 1, low byte fo r 16 bit color (see description on entry 0) 0 0x0754 C entry 2 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 2, high byte for 16 bit color; not used for 8 bit col or 0 0x0755 C entry 2 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 2, low byte fo r 16 bit color (see description on entry 0) 0 0x0756 C entry 3 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 3, high byte for 16 bit color; not used for 8 bit col or 0 0x0757 C entry 3 register bit function r/w description reset 7 ? 0 - r/w overwrite comparison register entry 3, low byte fo r 16 bit color (see description on entry 0) 0 TW8823 ? tft flat panel controller techwell, inc. 188 rev a 11/20/2009 0x0760 ~ 0x0762 source buffer memory starting addr ess[23:0] registers 0x0760 C high byte register bit function r/w description reset 7 ? 0 srcbfm0 _ast_hb r/w this register defines the source buffer memory starting address for osd block transfer; four bytes per increment. this register also serves as the memory starting ad dress in linear block transfer. 0 0x0761 C mid byte register bit function r/w description reset 7 ? 0 srcbfm0 _ast_mb r/w source buffer memory starting address for osd b lock transfer 0 0x0762 C low byte register bit function r/w description reset 7 ? 0 srcbfm0 _ast_lb r/w source buffer memory starting address for osd b lock transfer 0 0x0763 C source buffer memory horizontal length [7: 0] register bit function r/w description reset 7 ? 0 srcbfm0 _hl r/w define the source buffer memory horizontal wrap around length (64 pixels per increment; min length: 64 pixels; max length 2048 pixels) 0 0x0764 ~ 0x0765 transfer source horizontal start [1 0:0] registers 0x0764 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 srcsh_h b r/w define the horizontal offset from the source bu ffer memory starting location. (one pixel per increment). this register and the transfer source vertical star t register together specify the starting pixel location inside the source buffer memory for the bl ock transfer operation 0 0x0765 C low byte register bit function r/w description reset 7 ? 0 srcsh_l b r/w (see description above) 0 0x0766 ~ 0x0767 transfer source vertical start [10: 0] registers 0x0766 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 srcsv_h b r/w define the vertical offset from the source buff er memory starting location. (one line per increment) 0 0x0767 C low byte register bit function r/w description reset 7 ? 0 srcsv_l b r/w (see description above) 0 TW8823 ? tft flat panel controller techwell, inc. 189 rev a 11/20/2009 0x0768 ~ 0x0769 transfer horizontal length[11:0] re gisters 0x0768 C high byte register bit function r/w description reset 7 ? 4 - -- reserved. - 3 ? 0 srchl_h b r/w define the horizontal block length in block tra nsfer, block fill, or mcu/dma write operations. low byte (one pixel per increment, minimum is 1, ma ximum is 2048) 0 0x0769 C low byte register bit function r/w description reset 7 ? 0 srchl_l b r/w (see description above) 0 0x076a ~ 0x076b transfer vertical length[11:0] regi sters 0x076a C high byte register bit function r/w description reset 7 ? 4 - -- reserved. - 3 ? 0 srcvl_h b r/w define the vertical block length in block trans fer, block fill, or mcu/dma write operations. low byte (one line per increment, minimum is 1, max imum is 2048) 0 0x076b C low byte register bit function r/w description reset 7 ? 0 srcvl_l b r/w (see description above) 0 0x0770 ~ 0x0772 destination buffer memory starting address[23:0] registers 0x0770 C high byte register bit function r/w description reset 7 ? 0 dstbfm0 _ast_hb r/w destination buffer memory starting address for block transfer, block fill or mcu/dma write; four bytes per increment 0 0x0771 C mid byte register bit function r/w description reset 7 ? 0 dstbfm0 _ast_mb r/w (see description above) 0 0x0772 C low byte register bit function r/w description reset 7 ? 0 dstbfm0 _ast_lb r/w (see description above) 0 0x0773 C destination buffer memory horizontal lengt h[7:0] registers bit function r/w description reset 7 ? 0 dstbfm0 _hl r/w define the destination buffer memory horizontal wrap around length (64 pixels per increment; min length: 64 pixels; max length 2048 pixels) 0 TW8823 ? tft flat panel controller techwell, inc. 190 rev a 11/20/2009 0x0774 ~ 0x0775 transfer destination horizontal sta rt[10:0] registers 0x0774 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 dstsh_h b r/w define the horizontal offset from the destinati on buffer memory starting location. (one pixel per increment). this register and the transfer destination vertical start register together specify the starting pixel location inside the destination buffer memory for the block transfer, block fill, or mcu/dma write operations. 0 0x0775 C low byte register bit function r/w description reset 7 ? 0 dstsh_l b r/w (see description above) 0 0x0776 ~ 0x0777 transfer destination vertical start [10:0] registers 0x0776 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 dstsv_h b r/w define the vertical offset from the destination buffer memory starting location. (one line per increment) 0 0x0777 C low byte register bit function r/w description reset 7 ? 0 dstsv_l b r/w (see description above) 0 0x0778 C osd control register bit function r/w description reset 7 - 6 bltsel r/w blink timer interval selection 00: 32 frames 01: 16 frames 10: 8 frames 11: 4 fram es 0 5 flip r/w enable osd flip (upside down) display 0 4 mirror r/w enable osd mirror display 0 3 - 2 - r/w reserved. 1 fupdate r/w update osd window registers straight through set this bit to one and the register write operatio n of osd window 0, window 1, and window 4 takes effect right away 0 0 osdupd ate r/w update osd window registers on panel vsync after writing new values to osd window 0, window 1, and window4 registers and then write this bit to ?1?, the values of those register are updated on the next panel vsync self cleared to ?0? after update is done 0 TW8823 ? tft flat panel controller techwell, inc. 191 rev a 11/20/2009 0x0779 C osd gain control register bit function r/w description reset 7 ? 3 - r/w reserved 0000 0 2 ? 0 osdgain r/w osd gain value control for the blended osd 000: 1.0 100: 0.797 001: 0.953 101: 0.750 010: 0.906 110: 0.703 011: 0.859 111: 0.656 000 8 bit and 16 bit osd window each 8 bit osd window is associated with a look up table each table is organized as 256 x 32 bits bit composition: [31]: blink [30-24] : alpha value [23-16]: r [15-8]: g [7-0]: b window 0 and window 1 are designated as 8 bit osd window 0 does not blend with window 1 window 0 has higher priority over window 1 window 4 is designated as 16 bit osd 8 bit osd blends with 16 bit osd 0x077a C 8 bit osd look up table access control reg ister bit function r/w description reset 7 - 6 lutwin r/w this bit selects which look up table to access 00: look up table for window 0 01: look up table for window 1 1x: reserved 0 5 - 0 - r/w reserved. - 0x077b C 8 bit osd look up table address[7:0] regis ter bit function r/w description reset 7 ? 0 lutaddr r/w address pointer to the 256 x 32 l ook up table 0 TW8823 ? tft flat panel controller techwell, inc. 192 rev a 11/20/2009 0x077c ~ 0x077f 8 bit osd look up table data port[3 1:0] register 0x077c C byte 3 register bit function r/w description reset 7 ? 0 lutdin r/w write data to the look up table bi t [31:24] - 0x077d C byte 2 register bit function r/w description reset 7 ? 0 lutdin r/w write data to the look up table bi t [23:16] - 0x077e C byte 1 register bit function r/w description reset 7 ? 0 lutdin r/w write data to the look up table bi t [15:8] - 0x077f C byte 0 register bit function r/w description reset 7 ? 0 lutdin r/w write data to the look up table bi t [7:0] - 0x0780 C osd window 0 enable register bit function r/w description reset 7 ? 6 - -- reserved. - 5 win0_pe rpix r/w osd window 0 alpha blending selection 0: global window 0 alpha 1: per pixel alpha 0 4 win0_al pha_ena r/w osd window 0 alpha blending enable 0 3 - 1 - -- reserved. - 0 win0_en a r/w osd window 0 (8 bit) enable; priority is higher than osd window 1 0 0x0781 ~ 0x0782 osd window 0 horizontal start [10:0 ] registers 0x0781 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win0_hs _hb r/w osd window 0 horizontal start (offset from the lcd display first left pixel) high byte 0 0x0782 C low byte register bit function r/w description reset 7 ? 0 win0_hs _lb r/w osd window 0 horizontal start (offset from the lcd display first left pixel) low byte 0 TW8823 ? tft flat panel controller techwell, inc. 193 rev a 11/20/2009 0x0783 ~ 0x0784 osd window 0 vertical start [10:0] register 0x0783 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win0_vs _hb r/w osd window 0 verticall start (offset from the lcd display top first line) high byte 0 0x0784 C low byte register bit function r/w description reset 7 ? 0 win0_vs _lb r/w osd window 0 vertical start (offset from the l cd display top first line) low byte 0 0x0785 ~ 0x0786 osd window 0 horizontal length [11: 0] registers 0x0785 C high byte register bit function r/w description reset 7 ? 4 - -- reserved. - 3 ? 0 win0_hl_ hb r/w osd window 0 horizontal length high byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x0786 C low byte register bit function r/w description reset 7 ? 0 win0_hl_ lb r/w osd window 0 horizontal length low byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x0787 ~ 0x0788 osd window 0 vertical length [11:0 ] registers 0x0787 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win0_vl_ hb r/w osd window 0 vertical length high byte (one line per increment, minimum is 1, maximum is 2 048) 0 0x0788 C low byte register bit function r/w description reset 7 ? 0 win0_vl_ lb r/w osd window 0 vertical length low byte (one line per increment, minimum is 1, maximum is 2 048) 0 TW8823 ? tft flat panel controller techwell, inc. 194 rev a 11/20/2009 0x0789 ~ 0x078b osd window 0 buffer memory starting address [23:0] register 0x0789 C high byte register bit function r/w description reset 7 ? 0 bfm0_as t_hb r/w starting address of the buffer memory area allo cated for osd window 0; four bytes per increment 0 0x078a C mid byte register bit function r/w description reset 7 ? 0 bfm0_as t_mb r/w starting address of the buffer memory area allo cated for osd window 0 0 0x078b C low byte register bit function r/w description reset 7 ? 0 bfm0_as t_lb r/w starting address of the buffer memory area allo cated for osd window 0 0 0x078c C osd window 0 buffer memory horizontal leng th [7:0] register bit function r/w description reset 7 ? 0 bfm0_hl r/w define the window 0 buffer memory horizontal wr ap around length (64 pixels per increment; min length: 64 pixels; max length 2048 pixels) 0 0x078d C osd window 0 buffer memory vertical length [7:0] register bit function r/w description reset 7 ? 0 bfm0_vl r/w define the window 0 buffer memory vertical leng th (64 lines per increment; min length: 64 lines; max length 2048 lines) 0 0x078e ~ 0x078f osd window 0 image horizontal star t [10:0] registers 0x078e C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm0_h s_hb r/w define the horizontal offset of the osd window 0 image in the buffer memory (referenced to the window 0 buffer memory starting location; one pixel per increment) 0 0x078f C low byte register bit function r/w description reset 7 ? 0 wfm0_h s_lb r/w (see description above) 0 TW8823 ? tft flat panel controller techwell, inc. 195 rev a 11/20/2009 0x0790 ~ 0x0791 osd window 0 image vertical start [ 10:0] register 0x0790 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm0_vs _hb r/w define the vertical offset of the osd window 0 image in the buffer memory (referenced to the window 0 buffer memory starting location; one line per increment) 0 0x0791 C low byte register bit function r/w description reset 7 ? 0 wfm0_vs _lb r/w (see description above) 0 0x0792 C osd window 0 global alpha value [6:0] regi ster bit function r/w description reset 7 - r/w reserved. 6 ? 0 win0_al pha r/w osd window 0 global alpha blending value min: 0x00 max osd window 0 shown after blending max: 0x7f no osd window 0 shown after blending 0 0x07a0 C osd window 1 enable register bit function r/w description reset 7 ? 6 - -- reserved. - 5 win1_pe rpix r/w osd window 1 alpha blending selection 0: global window 1 alpha 1: per pixel alpha 0 4 win1_al pha_ena r/w osd window 1 alpha blending enable 0 3 - 1 - -- reserved. - 0 win1_en a r/w osd window 1 (8 bit) enable; priority is lower than osd window 0 0 0x07a1 ~ 0x07a2 osd window 1 horizontal start [10:0 ] registers 0x07a1 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win1_hs _hb r/w osd window 1 horizontal start (offset from the lcd display first left pixel) high byte 0 0x07a2 C low byte register bit function r/w description reset 7 ? 0 win1_hs _lb r/w osd window 1 horizontal start (offset from the lcd display first left pixel) low byte 0 TW8823 ? tft flat panel controller techwell, inc. 196 rev a 11/20/2009 0x07a3 ~ 0x07a4 osd window 1 vertical start [10:0] registers 0x07a3 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win1_vs _hb r/w osd window 1 vertical start (offset from the l cd display top first line) high byte 0 0x07a4 C low byte register bit function r/w description reset 7 ? 0 win1_vs _lb r/w osd window 1 vertical start (offset from the l cd display top first line) low byte 0 0x07a5 ~ 0x07a6 osd window 1 horizontal length [11 :0] registers 0x07a5 C high byte register bit function r/w description reset 7 ? 4 - -- reserved. - 3 ? 0 win1_hl_ hb r/w osd window 1 horizontal length high byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x07a6 C low byte register bit function r/w description reset 7 ? 0 win1_hl_ lb r/w osd window 1 horizontal length low byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x07a7 ~ 0x07a8 osd window 1 vertical length [11:0 ] registers 0x07a7 C high byte register bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win1_vl_ hb r/w osd window 1 vertical length high byte (one line per increment, minimum is 1, maximum is 2 048) 0 0x07a8 C low byte register bit function r/w description reset 7 ? 0 win1_vl_ lb r/w osd window 1 vertical length low byte (one line per increment, minimum is 1, maximum is 2 048) 0 TW8823 ? tft flat panel controller techwell, inc. 197 rev a 11/20/2009 0x07a9 ~ 0x07ab osd window 1 buffer memory starting address [23:0] registers 0x07a9 C high byte register bit function r/w description reset 7 ? 0 bfm1_as t_hb r/w starting address of the buffer memory area allo cated for osd window 1; four bytes per increment 0 0x07aa C mid byte register bit function r/w description reset 7 ? 0 bfm1_as t_mb r/w starting address of the buffer memory area allo cated for osd window 1 0 0x07ab C low byte register bit function r/w description reset 7 ? 0 bfm1_as t_lb r/w starting address of the buffer memory area allo cated for osd window 1 0 0x07ac C osd window 1 buffer memory horizontal leng th [7:0] register bit function r/w description reset 7 ? 0 bfm1_hl r/w define the window 1 buffer memory horizontal wr ap around length (64 pixels per increment; min length: 64 pixels; max length 2048 pixels) 0 0x07ad C osd window 1 buffer memory vertical length [7:0] register bit function r/w description reset 7 ? 0 bfm1_vl r/w define the window 1 buffer memory vertical leng th (64 lines per increment; min length: 64 lines; max length 2048 lines) 0 0x07ae ~ 0x07af osd window 1 image horizontal start [10:0] register 0x07ae C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm1_h s_hb r/w define the horizontal offset of the osd window 1 image in the buffer memory (referenced to the window 0 buffer memory starting location; one pixel per increment) 0 0x07af C low byte register bit function r/w description reset 7 ? 0 wfm1_h s_lb r/w (see description above) 0 TW8823 ? tft flat panel controller techwell, inc. 198 rev a 11/20/2009 0x07b~ 0x07b1 osd window 1 image vertical start [10 :0] registers 0x07b0 C high byte register bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm1_vs _hb r/w define the vertical offset of the osd window 1 image in the buffer memory (referenced to the window 0 buffer memory starting location; one line per increment) 0 0x07b1 C low byte register bit function r/w description reset 7 ? 0 wfm1_vs _lb r/w (see description above) 0 0x07b2 C osd window 1 global alpha value [6:0] regi ster bit function r/w description reset 7 - r/w reserved. 6 ? 0 win1_al pha r/w osd window 1 global alpha blending value min: 0x00 max osd window 1 shown after blending max: 0x7f no osd window 1 shown after blending 0 0x07c0 C osd window 4 enable bit function r/w description reset 7 rev_cbr r/w interchange the position of cb with the cr?s wh en the data format ?osd16form? is ycbcr422 or ycbcr655 0: normal position (y8cb8, y8cr8), (y6, cb5, cr5) 1: reverse position (y8cr8, y8cb8), (y6, cr5, cb5) 0 6 - -- reserved. 0 5 win4_pe rpix r/w osd window 4 alpha blending selection 0: global window 4 alpha 1: for rgb4444 this bit select individual alpha; fo r the other formats this bit enable the color key alpha blending 0 4 win4_al pha_ena r/w osd window 4 alpha blending enable 0 3 - 1 osd16fo rm -- format selection for osd window 4: 000: ycbcr422 (y8cb8, y8cr8) data0[15:0] = {y1 [7:0], cb1[7:0]} data1[15:0] = {y2[7:0], cr2[7: 0]} 001: rgb565 (r 5, g 6, b 5) data[15:0] = {r[4:0], g[5:4],g[3:0],b[4:0]} 010: rgb4444 (alpha 4, r 4, g 4, b 4) data[15:0] = {a[3:0],r[3:0],g[3:0],b[3:0]} 011: rgb1555 (blink 1, r 5, g 5, b 5) data[15:0] = {bl, r[4:0],g[4:0],b[4:0]} 100: ycbcr655 (y 6, cb 5, cr 5) data[15:0] = {y[5: 0],cb[4:0],cr[4:0]} 0 0 win4_en a r/w osd window 4 (16 bit) enable 0 TW8823 ? tft flat panel controller techwell, inc. 199 rev a 11/20/2009 0x07c1 ~ 0x07c2 osd window 4 horizontal start [10: 0] 0x07c1 C high byte bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win4_hs _hb r/w osd window 4 horizontal start (offset from the lcd display first left pixel) high byte 0 0x07c2 C low byte bit function r/w description reset 7 ? 0 win4_hs _lb r/w osd window 4 horizontal start (offset from the lcd display first left pixel) low byte 0 0x07c3 ~ 0x07c4 osd window 4 vertical start [10:0] 0x07c3 C high byte bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win4_vs _hb r/w osd window 4 vertical start (offset from the l cd display top first line) high byte 0 0x07c4 C low byte bit function r/w description reset 7 ? 0 win4_vs _lb r/w osd window 4 vertical start (offset from the l cd display top first line) low byte 0 0x07c5 ~ 0x07c6 osd window 4 horizontal length [11 :0] 0x07c5 C high byte bit function r/w description reset 7 ? 4 - -- reserved. - 3 ? 0 win4_hl_ hb r/w osd window 4 horizontal length high byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x07c6 C low byte bit function r/w description reset 7 ? 0 win4_hl_ lb r/w osd window 4 horizontal length low byte (one pixel per increment, minimum is 1, maximum is 2048) 0 TW8823 ? tft flat panel controller techwell, inc. 200 rev a 11/20/2009 0x07c7 ~ 0x07c8 osd window 4 vertical length [11:0 ] 0x07c7 C high byte bit function r/w description reset 7 ? 3 - -- reserved. - 2 ? 0 win4_vl_ hb r/w osd window 4 vertical length high byte (one line per increment, minimum is 1, maximum is 2 048) 0 0x07c8 C low byte bit function r/w description reset 7 ? 0 win4_vl_ lb r/w osd window 4 vertical length low byte (one line per increment, minimum is 1, maximum is 2 048) 0 0x07c9 ~ 0x07cb window 4 buffer memory starting ad dress [23:0] 0x07c9 C high byte bit function r/w description reset 7 ? 0 bfm4_as t_hb r/w starting address of the buffer memory area allo cated for osd window 4; four bytes per increment 0 0x07ca C mid byte bit function r/w description reset 7 ? 0 bfm4_as t_mb r/w starting address of the buffer memory area allo cated for osd window 4 0 0x07cb C low byte bit function r/w description reset 7 ? 0 bfm4_as t_lb r/w starting address of the buffer memory area allo cated for osd window 4 0 0x07cc C osd window 4 buffer memory horizontal leng th [7:0] bit function r/w description reset 7 ? 0 bfm4_hl r/w define the window 4 buffer memory horizontal wr ap around length (64 pixels per increment; min length: 64 pixels; max length 2048 pixels) 0 0x07cd C osd window 4 buffer memory vertical length [7:0] bit function r/w description reset 7 ? 0 bfm4_vl r/w define the window 4 buffer memory vertical leng th (64 lines per increment; min length: 64 lines; max length 2048 lines) 0 TW8823 ? tft flat panel controller techwell, inc. 201 rev a 11/20/2009 0x07ce ~ 0x07cf osd window 4 image horizontal start [10:0] 0x07ce C high byte bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm4_h s_hb r/w define the horizontal offset of the osd window 4 image in the buffer memory (referenced to the window 0 buffer memory starting location; one pixel per increment) 0 0x07cf C low byte bit function r/w description reset 7 ? 0 wfm4_h s_lb r/w (see description above) 0 0x07d0 ~ 0x07d1 osd window 4 image vertical start [10:0] 0x07d0 C high byte bit function r/w description reset 7 ? 3 - r/w reserved. 2 ? 0 wfm4_vs _hb r/w osd window 4 buffer memory vertical start 0 0x07d1 C low byte bit function r/w description reset 7 ? 0 wfm4_vs _lb r/w define the vertical offset of the osd window 4 image in the buffer memory (referenced to the window 0 buffer memory starting location; one line per increment) 0 0x07d2 C osd window 4 global alpha value [6:0] ]] ] bit function r/w description reset 7 - r/w reserved. 6 ? 0 win4_al pha r/w osd window 4 global alpha blending value min: 0x00 max osd window 4 shown after blending max: 0x7f no osd window 4 shown after blending 0 TW8823 ? tft flat panel controller techwell, inc. 202 rev a 11/20/2009 0x07d4 ~ 0x07d5 color key 0 for 16 bit osd [15:0] 0x07d4 C high byte bit function r/w description reset 7 ? 0 ckey0_h b r/w color key # 0 high byte 0 0x07d5 C low byte bit function r/w description reset 7 ? 0 ckey0_l b r/w color key # 0 low byte 0 0x07d6 ~ 0x07d7 color key 1 for 16 bit osd [15:0] 0x07d6 C high byte bit function r/w description reset 7 ? 0 ckey1_h b r/w color key # 1 high byte 0 0x07d7 C low byte bit function r/w description reset 7 ? 0 ckey1_l b r/w color key # 1 low byte 0 0x07d8 ~ 0x07d9 color key 2 for 16 bit osd [15:0] 0x07d8 C high byte bit function r/w description reset 7 ? 0 ckey2_h b r/w color key # 2 high byte 0 0x07d9 C low byte bit function r/w description reset 7 ? 0 ckey2_l b r/w color key # 2 low byte 0 0x07da ~ 0x07db color key 3 for 16 bit osd [15:0] 0x07da C high byte bit function r/w description reset 7 ? 0 ckey3_h b r/w color key # 3 high byte 0 0x07db C low byte bit function r/w description reset 7 ? 0 ckey3_l b r/w color key # 3 low byte 0 TW8823 ? tft flat panel controller techwell, inc. 203 rev a 11/20/2009 0x07dc C color key 0 alpha value [6:0] bit function r/w description reset 7 - r/w reserved. 6 ? 0 key_alp ha0 r/w alpha blending value for color key # 0 0 0x07dd C color key 1 alpha value [6:0] bit function r/w description reset 7 - r/w reserved. 6 ? 0 key_alp ha1 r/w alpha blending value for color key # 1 0 0x07de C color key 2 alpha value [6:0] bit function r/w description reset 7 - r/w reserved. 6 ? 0 key_alp ha2 r/w alpha blending value for color key # 2 0 0x07df C color key 3 alpha value [6:0] bit function r/w description reset 7 - r/w reserved. 6 ? 0 key_alp ha3 r/w alpha blending value for color key # 3 0 TW8823 ? tft flat panel controller techwell, inc. 204 rev a 11/20/2009 osd interrupt enable, vertical active status 0x07f0 C vertical active status bit function r/w description reset 7-6 - r/w reserved. 0 5 disp_ate r/w display vertical active status: set by the display vertical active ending edge reset by writing a ?1? to this bit. - 4 osd_ate r/w osd window active status: set by the osd window active ending edge reset by writing a ?1? to this bit - 3 win4_at r osd window 4 vertical active status - 2 - r/w reserved. - 1 win1_at r osd window 1 vertical active status - 0 win0_at r osd window 0 vertical active status - 0x07f1 C osd busy interrupt enable bit function r/w description reset 7 osd_w_ mask0 r/w mask (disable) host interrupt by the osg operatio n busy, 0x0701[7] 1: mask on 0: mask off 0 6 osd_w_ mask1 r/w mask (disable) host interrupt by the osg fifo bus y, 0x0701[6] 1: mask on 0: mask off 0 5 disp_ate _mask r/w mask (disable) host interrupt by the display acti ve status, 0x07f0[5] 1: mask on 0: mask off 0 4 osd_ate _mask r/w mask (disable) host interrupt by the osd active s tatus, 0x07f0[4] 1: mask on 0: mask off 0 3-0 - r/w reserved. 0 main/sub path osd selection 0x07f8 C main/sub path osd selection bit function r/w description reset 7:6 - r/w reserved 0 5:4 sub_sel r/w sub path (in dual view) osd selection 00: no osd 01:: 8-bit osd 10: 16-bit osd 11: 8-bit and 16-bit osd 0 3:2 - r/w reserved 0 main_se l r/w main path osd selection 00: no osd 01:: 8-bit osd 10: 16-bit osd 11: 8-bit and 16-bit osd 0 TW8823 ? tft flat panel controller techwell, inc. 205 rev a 11/20/2009 external osd 0x08f2C external osd control bit function r/w description reset 7 eosd_m ode r/w external osd clock mode 0: clock is on all the time 1: clock is on during the horizontal active region plus two times of 0x08f2[3:1] the horizontal active is determined by 0x08f3[0 ] 1 6 eosd_vs _pol r/w external osd vs polarity control 0: active high, 1: active low 0 5 eosd_hs _pol r/w external osd hs polarity control 0: active high, 1: active low 0 4 eosd_ck _pol r/w external osd clock polarity control 0: falling edge, 1: rising edge 0 3 ? 1 eosddel ay r/w external osd access latency control 0 0 osd_po rten r/w external osd port enable/disable 0: disable, 1: enable 0 0x08f3 C external osd horizontal control bit function r/w description reset 7 ? 2 eosd_hs _pw -- external osd hs pulse width [5:0] 0: one eoclk 1: two eoclk ? 63: sixty-four eoclk ? 0 1 exsync_ sel r/w external osd sync mode selection 0: external osd pins eovs/eohs are derived from vac tive/hactive the hactive is further determined by 0x08f3[0] 1: external osd pins eovs/eohs are derived from pan el vsync/hsync 0 0 exhact_ sel r/w horizontal active selection 0: use internal osd window 0 horizontal active 1: use panel hactive 0 0x08f4 C external osd clock output delay bit function r/w description reset 7 - -- reserved. - 6 ? 4 ocktps r/w external osd clock eoclk delay time selection. 000: no delay time inserted. each increment increas es the delay by 1 ns. 0 3 - 0 - -- reserved. - 0x08f5 C external osd alpha blending level bit function r/w description reset 7 ena_ea_ pin -- enable external_alpha_blending pin input. 0: the blending is on 1: the blending on/off is controlled by the pin 0 6 ? 5 - -- reserved. - 4 ? 0 ext_alp ha r/w external osd alpha-blending level control. 0: max external osd shown 0 TW8823 ? tft flat panel controller techwell, inc. 206 rev a 11/20/2009 0x08f6 C external osd misc control bit function r/w description reset 7 - r/w reserved. - 6 - 4 eoden_d ly r/w external osd input data enable signal delay : 0 ~ 7 clock cycle delay 0 3 - 0 - r/w reserved. - 0x08f7 C external osd vsync pulse width bit function r/w description reset 7:4 - r/w reserve - 3:0 eosd_vs _pw r/w external osd vs pulse width 0: one eosd hs period 1: two eosd hs periods ? 15: sixteen eosd hs periods 0 TW8823 ? tft flat panel controller techwell, inc. 207 rev a 11/20/2009 lcdc C gamma & dither & key (waver_top) 0x0900 C lcdc gamma control register bit function r/w description reset 7 gamae_r r/w enable red gamma correction. 0 6 gamae_g r/w enable green gamma correction. 0 5 gamae_b r/w enable blue gamma correction. 0 4 reserved - reserved - 3 - 2 auto_inc r/w enable gamma table address auto increment for readi ng/writing gamma data port. 0 = disable 1 = read only 2 = write only 3 = read/write 0 1 - 0 gamma_rgb _indx r/w gamma tables access selection: index address 0x1f1 to 0x1f2 are used for gamma tab le accesses. there are 3 sets of gamma table, one table for one color, sharing the s ame address port and data port. these 2 bits identifies which table is accessed. 0 = rgb gamma table 1 = red gamma table 2 = green gamma table 3 = blue gamma table 0 0x0901 C gamma table address port register bit function r/w description reset 7 - 0 gamma_ra m- starting_a ddr r/w gamma table address port. 00 0x0902 C gamma table data port register bit function r/w description reset 7 - 2 reserved - reserved - 1 - 0 gamma_ra m_data[9:8] r/w gamma table data port (upper bits) 0 0x0903 C gamma table data port register bit function r/w description reset 7-0 gamma_ra m_data[7:0] r/w gamma table data port (lower bits) 00 TW8823 ? tft flat panel controller techwell, inc. 208 rev a 11/20/2009 0x0910 C dither option register bit function r/w description reset 7 reserved - reserved 6-4 dither_opt ion r/w dither option code "0 10" is recommended for 6:6:6 output 0 00 3 reserved - reserved - 2-0 dither_for mat r/w dither output format selection "001" is recommended for 6:6:6 output 000 dither output selection and calculations dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method 001 (5) (5) (5) 2x2 010 (5,4) (5,4) (5,4) 2x2 000 8:8:8 000 n/a none 011 (5,4,3) (5,4,3) (5,4,3) 2x2 001 (3) (3) (3) 2x2 100 4:4:4 100 (5,4,3,2) (5,4,3,2) (5,4,3,2) 4x4 010 (3,2) (3,2)(3,2) 2x2 001 (6) (6) (6) 2x2 011 (3,2,1) (3,2,1)(3,2,1) 2x2 010 (6,5) (6,5) (6,5) 2x2 001 6:6:6 100 (3,2,1,0) (3,2,1,0)(3,2,1,0) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 001 (4) (3) (4) 2x2 101 3:3:3 100 (6,5,4,3) (6,5,4,3) (6,5,4,3) 4x4 010 (4,3) (3,2) (4,3) 2x2 001 (6) (6) (7) 2x2 011 (4,3,2) (3,2) (4,3,2) 2x2 010 (6,5) (6,5) (7,6) 2x2 010 5:6:5 100 (4,3,2,1) (3,2,1) (4,3,2,1) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 001 (4) (4) (4) 2x2 110 3:3:2 100 (6,5,4,3) (6,5,4,3) (7,6,5,4) 4x4 010 (4,3) (4,3) (4,3) 2x2 011 (4,3,2) (4,3,2) (4,3,2) 2x2 011 5:5:5 100 (4,3,2,1) (4,3,2,1) (4,3,2,1) 4x4 TW8823 ? tft flat panel controller techwell, inc. 209 rev a 11/20/2009 0x0920 C rgb level readout register bit function r/w description reset 7-0 rdkeypos_ x r/w color level readout position x [7:0] (lsb) 00 0x0921 C rgb level readout register bit function r/w description reset 7-0 rdkeypos_ y r/w color level readout position y [7:0] (lsb) 00 0x0922 C rgb level readout register bit function r/w description reset 7 reserved - reserved - 6-4 rdkeypos_ y[10:8] r/w color level readout position y [10:8] (msb) 0 3-0 rdkeypos_ x[11:8] r/w color level readout position x [11:8] (msb) 0 0x0923 C pip alpha blending red key register bit function r/w description reset 7-0 keyrdr r/w red key color level for pip alpha blending 00 0x0924 C pip alpha blending green key register bit function r/w description reset 7-0 keyrdg r/w green key color level for pip alpha blending 00 0x0925 C pip alpha blending blue key register bit function r/w description reset 7-0 keyreb r/w blue key color level for pip alpha blending 00 TW8823 ? tft flat panel controller techwell, inc. 210 rev a 11/20/2009 lcdc C tga & power management 0x0970 C panel interface control register bit function r/w description reset 7 reserved - reserved 0 6 fpdeah r/w set fpde active high 0: ac tive low 1 5 fphsah r/w set fphs active high 0: ac tive low 0 4 fpvsah r/w set fpvs active high 0: ac tive low 0 3 rvfpck r/w invert fpclk polarity 0: output signals to flat panel (fpvs, fphs, ? etc. ) are referenced to the falling edge of fpclk. 0 2 reserved - reserved 0 1 rvbit r/w reverse the bit order on panel data bus. 0: msb is on fpr0[7], fpg0[7], fpb0[7] 1: msb is on fpr0[0], fpg0[0], fpb0[0] 0 0 reserved - reserved 0 0x0971 C panel clock delay register bit function r/w description reset 7 ? 3 reserved - reserved 2 ? 0 fpclk_del ay r/w panel clock fpclk delay time selection. 000: no delay time inserted. each increment increas es the delay by 1 ns. 0 0x0987 C pwm control register bit function r/w description reset 7 ? 6 reserved - reserved 0 5 pwmen r/w enable for pwm 0 4 pwmal r/w active low for pwm 0 3 ? 0 reserved - reserved 0 0x0988 C pwm control register bit function r/w description reset 7 ? 0 pwm_cnt r/w positive pulse width of the pwm. if this register has an ?n? value, the positive pul se width duration is ?n+1? pwm clocks. 40h 0x0989 ~ 0x098a pwm clock divider registers 0x0989 C high byte register bit function r/w description reset 7 ? 2 reserved - reserved 0 1 ? 0 pwm_divnu m [9:8] r/w clock divider for pwm - high 0 TW8823 ? tft flat panel controller techwell, inc. 211 rev a 11/20/2009 0x098a C low byte register bit function r/w description reset 7 ? 0 pwm_divnu m [7:0] r/w clock divider for pwm ? low this register divides the 27 mhz clock down to driv e pwm counter 0 0x098b C pwm2 control register bit function r/w description reset 7 ? 6 reserved - reserved 0 5 pwm2en r/w enable for pwm2 0 4 pwm2al r/w active low for pwm2 0 3 ? 0 reserved - reserved 0 0x098c C pwm2 control register bit function r/w description reset 7 ? 6 pwm2_cnt r/w positive pulse width of the pwm 2. if this register has an ?n? value, the positive pul se width duration is ?n+1? pwm2 clocks. 40h 0x098d ~ 0x098e pwm2 clock divider registers 0x098d C high byte register bit function r/w description reset 7 ? 2 reserved - reserved 0 1 ? 0 pwm2_divn um [9:8] r/w clock divider for pwm2 - high 0 0x098e C low byte register bit function r/w description reset 7 ? 0 pwm2_divn um [7:0] r/w clock divider for pwm2 ? low this register divides the 27 mhz clock down to driv e pwm2 counter 0 0x09f5 C panel power pin register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 fpbias r/w set the fpbias pin value to high or lo w 0 1 eppwr r/w set the fppwc pin value to high or low 0 0 efpif r/w enable the output driver of the panel int erface signals 1: output enable 0: output tristated 0 TW8823 ? tft flat panel controller techwell, inc. 212 rev a 11/20/2009 lcdc timing controller configuration registers 0x0a00 C output mode control register bit function r/w description reset 7 reserved - reserved --- 6 tcck_ph r/w tcclk phase control if reg0x300[0] set is high. (divide clock mode) 0 : no clock phase shift 1 : clock phase 90 degree shift *** it?s set reg0x270[3] (invert clock polarity) hi gh and this bit set high also then tcclk is 270 degree shift . 0 5 roe_en r/w roe (row driver) output enable 0 : disable 1 : enable 0 4-2 reserved - reserved -- 1 tcons r/w 0 : disable tcon 1 : enable tcon 0 0 div_ck r/w output mode selection 0 : one pixel data out per tcclk 1 : two pixel data out per tcclk (rising and fallin g both) 0 0x0a01 C display control register bit function r/w description reset 7 reserved - reserved --- 6 reserved - reserved 0 5 reserved - reserved 0 4 reserved - reserved 0 3 rev_en r/w pixel data reverse control 0 : data no reverse (don?t case tcrev signal) 1 : data reverse if tcrev signal is high period 0 2 reserved - reserved --- 1-0 inv r/w inversion mode selection 2?b00 : disable 2 ?b01 : disable 2?b10 : line inversion 2?b1 1 : frame inversion 00 0x0a02 C display direction control register bit function r/w description reset 7-4 reserved - reserved --- 3-2 top_btm r/w top/bottom display direction select 2?b00 : top low active (normal) 2?b01 : top high active (normal) 2?b10 : bottom low active (flip) 2?b11 : bottom high active (flip) 00 1-0 lft_rht r/w left/right display direction select 2?b00 : left low active (normal) 2?b01 : left high active (normal) 2?b10 : right low active (mirror) 2?b11 : right high active (mirror) 11 TW8823 ? tft flat panel controller techwell, inc. 213 rev a 11/20/2009 0x0a03 C control signal polarity selection register bit function r/w description reset 7-6 reserved - reserved ---- 5 pol_con r/w tcon polarity swap control 0 4 rck_p r/w row driver clock signal 0 : active low 1 : active high 0 3 roe_p r/w row driver output enable signal 0 : active low 1 : active high 0 2 rsp_p r/w row driver start pulse signal 0 : active low 1 : active high 1 1 clp_p r/w column driver latch pulse signal 0 : active low 1 : active high 1 0 csp_p r/w column driver start pulse signal 0 : active low 1 : active high 1 0x0a04 C control signal generation method register bit function r/w description reset 7 reserved - reserved - 6 reserved - reserved - 5 pgm_rck r/w row driver clock signal 1 4 pgm_roe r/w row driver output enable signal 0 : this is generate during horizontal display e nable. 1 : it?s generated that set tcon register address 0x32c though 0x32f. also, this is relative to vertical active re gister 0x30c though 0x30f. 1 3 pgm_rsp r/w row driver start pulse signal 0 : this signal immediately generate and then kee p one horizontal period activation received from vertical act ive signal. 1 : it?s generated that set tcon register address 0x324 though 0x327. also, this is relative to vertical back porc h register 0x279. 0 2 pgm_pol r/w 0 : this signal toggles when hsync toggle. 1: it?s generated that set tcon register 0x310 thro ugh 0x311 1 1 pgm_clp r/w column driver latch pulse signal 0 : this signal generate after horizontal display enable done a every scan line. 1 : it?s generated that set tcon register address 0x312 though 0x315. 0 0 pgm_csp r/w column driver start pulse signal 0 : this signal generate after horizontal display enable. 1 : it?s generated that set tcon register address 0x31a though 0x31d. also, this is relative to horizontal back por ch register 0x274. 0 TW8823 ? tft flat panel controller techwell, inc. 214 rev a 11/20/2009 0x0a06 C panel type select register bit function r/w description reset 7-3 reserved - reserved --- 2 frc_dac_in v r/w 1 : force dac output always inverted 0 : normal dac output and inversion is based on polarity signal 0 1 rev_inv r/w signal output selection 0 : tcinv signal output select 1 : tcrev output select 1 0 line_inv r/w analog panel data swapping 0 : no data inversion 1 : every line data inversion 0 0x0a0a C special lcd module control register bit function r/w description reset 7 kp_sel r/w 1 : enable instruction mode, 0 : nor mal mode 0 6 kp_ena r/w enable kopin mode 0 5-4 rsp_width r/w row driver start pulse width (period) selection 0 : one horizontal period 1 : two horizontal period 2 : three horizontal period 3 : four horizontal period 00 3-2 reserved - reserved -- 1-0 company r/w lcd module company selection 2?b00 : lg-philips lcd module 2?b01 : sharp lcd module 2?b10, 2?b11 : other companies lcd module 10 0x0a0b C revv(tcpolp) / revc(tcpoln) control regist er bit function r/w description reset 7-0 revv_revc r/w revv_revc[7 :0] for sharp 4dh 0x0a0c C vertical active start high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 v_st[11:8] r/w ver_ash[11:8] 0h 0x0a0d C vertical active start low register bit function r/w description reset 7-0 v_st[7:0] r/w ver_asl[7:0] 00h 0x0a0e C vertical active end high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 v_ed[11:8] r/w ver_aeh[11:8] 02h 0x0a0f C vertical active end low register bit function r/w description reset 7-0 v_ed[7:0] r/w ver_ael[7:0] 94h TW8823 ? tft flat panel controller techwell, inc. 215 rev a 11/20/2009 column driver chip control signals relative registe rs 0x0a10 C polarity control high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 cp_sw[11:8] r/w programmable polarity period high[1 1:8] value. 0h 0x0a11 C polarity control low register bit function r/w description reset 7-0 cp_sw[7:0] r/w programmable polarity period low[7:0 ] value. 00h 0x0a12 C load/latch pulse start high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 clp_st[11:8] r/w lp_hsh[11:8] 00h 0x0a13 C load/latch pulse start low register bit function r/w description reset 7-0 clp_st[7:0] r/w lp_hsl[7 :0] 24h 0x0a14 C load/latch pulse width high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 clp_ed[11:8] r/w lp_heh[11:8] 0h 0x0a15 C load/latch pulse width low register bit function r/w description reset 7-0 clp_ed[7:0] r/w lp_hel[7:0] 02h 0x0a1a C column driver start pulse high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 csp_st[11:8] r/w sp_hsh[11:8] 0h 0x0a1b C column driver start pulse low register bit function r/w description reset 7-0 csp_st[7:0] r/w sp_hsl[7 :0] 3ch 0x0a1c C column driver start pulse width high regis ter bit function r/w description reset 7-4 reserved - reserved --- 3-0 csp_ed[11:8] r/w sp_heh[11 :8] 0h 0x0a1d C column driver start pulse width low regist er bit function r/w description reset 7-0 csp_ed[7:0] r/w sp_hel[7 :0] 01h TW8823 ? tft flat panel controller techwell, inc. 216 rev a 11/20/2009 row driver chip control signals relative registers 0x0a20 C clock start pulse high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 rck_st[11:8] r/w rck_hsh[11:8] 0 0x0a21 C clock start pulse low register bit function r/w description reset 7-0 rck_st[7:0] r/w rck_hsl[7 :0] 64h 0x0a22 C clock start pulse width high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 rck_ed[11:8] r/w rck_heh[11 :8] 01h 0x0a23 C clock start pulse width low register bit function r/w description reset 7-0 rck_ed[7:0] r/w rck_hel[7 :0] f4h 0x0a24 C row start pulse high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 rsp_st[11:8] r/w rsp_vsh[11:8] 0h 0x0a25 C row start pulse low register bit function r/w description reset 7-0 rsp_st[7:0] r/w rsp_vsl[7 :0] 37h 0x0a26 C row start pulse width high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 rsp_ed[11:8] r/w rsp_veh[11 :8] 0h 0x0a27 C row start pulse width low register bit function r/w description reset 7-0 rsp_ed[7:0] r/w rsp_vel[7 :0] 01h 0x0a2c C row output enable high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 roe_st[11:8] r/w roe_hsh[11:8] 0 0x0a2d C row output enable low register bit function r/w description reset 7-0 roe_st[7:0] r/w roe_hsl[7 :0] 0ah TW8823 ? tft flat panel controller techwell, inc. 217 rev a 11/20/2009 0x0a2e C row output enable width high register bit function r/w description reset 7-4 reserved - reserved --- 3-0 roe_ed[11:8] r/w roe_heh[11 :8] 0 0x0a2f C row output enable width low register bit function r/w description reset 7-0 roe_ed[7:0] r/w roe_hel[7 :0] 36h 0x0a34 C sharp mode register bit function r/w description reset 7-4 reserved - reserved 3-0 sharp_str_ h r/w sharp same polarity start point high bits 0h 0x0a35 C sharp mode register bit function r/w description reset 7-0 sharp_str_ l r/w sharp same polarity start point low bits 20h 0x0a36 C sharp mode register bit function r/w description reset 7-4 reserved - reserved --- 3-0 sharp_end_ h r/w sharp same polarity end point high bits 1h 0x0a37 C sharp mode register bit function r/w description reset 7-0 sharp_end_ l r/w sharp same polarity end point low bits e2h 0x0a38 C direct mode tclp width, position and step control register bit function r/w description reset 7 clpfb r/w direct mode tclp front/back position se lection 0 6 reserved - reserved --- 5-4 clpw r/w direct mode tclp width control 1h 3 reserved - reserved --- 2-0 clpsel r/w direct mode tclp position step contr ol 5h 0x0a39 C direct mode tcsp width and step control re gister bit function r/w description reset 7-6 reserved - reserved --- 5-4 cspw r/w direct mode tcsp width control 0 3 reserved - reserved --- 2-0 cspsel r/w direct mode tcsp position step contr ol 1h 0x0a3a C polarity special function register bit function r/w description reset 7-6 reserved - reserved --- 5 pol_h_ena r/w enable polarity h-inversion only mo de 0 4 pol_h_val r/w polarity h-inversion only mode init ial value 0 3-0 pol_step r/w tcpol direct mode 16 step control 0h TW8823 ? tft flat panel controller techwell, inc. 218 rev a 11/20/2009 0x0a3d C direct mode trsp step control register bit function r/w description reset 7-6 reserved - reserved --- 5-0 trsp_step r/w direct mode trsp 64 step control 0h 0x0a3f C delta rgb register bit function r/w description reset 7-5 reserved - reserved --- 4 line_con r/w delta rgb line control 0 3-2 sync_con r/w delta rgb sync control 0 1 delta_line_ con r/w 0 : odd line mix, 1 : even line mix 0 0 delta_line_ en r/w enable delta rgb line mix 0 TW8823 ? tft flat panel controller techwell, inc. 219 rev a 11/20/2009 lcdc C input measurement 0x0b00 ~ 0x0b01 measurement window horizontal sta rt [10:0] 0x0b00 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 ? 0 mea_win_h_ st [10:8] r/w input measurement window definition: horizontal start - high 0 0x0b01 C low byte register bit function r/w description reset 7 ? 0 mea_win_h_ st [7:0] r/w input measurement window definition: horizontal start - low 20h 0x0b02 ~ 0x0b03 measurement window horizontal len gth [11:0] 0x0b02 C high byte register bit function r/w description reset 7 ? 4 reserved - reserved 0 3 ? 0 mea_win_h_ len [11:8] r/w input measurement window definition: horizontal length - high 1 0x0b03 C low byte register bit function r/w description reset 7 ? 0 mea_win_h_ st [7:0] r/w input measurement window definition: horizontal length - low e0h 0x0b04 ~ 0x0b05 measurement window vertical start [10:0] 0x0b04 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 ? 0 mea_win_v_ st [10:8] r/w input measurement window definition: vertical start - high 0 0x0b05 C low byte register bit function r/w description reset 7 ? 0 mea_win_v_ st [7:0] r/w input measurement window definition: horizontal start - low 20h TW8823 ? tft flat panel controller techwell, inc. 220 rev a 11/20/2009 0x0b06 ~ 0x0b07 measurement window vertical lengt h [10:0] 0x0b06 C high byte register bit function r/w description reset 7 ? 3 reserved - reserved 0 2 ? 0 mea_win_v_ len [10:8] r/w input measurement window definition: verticall length - high 0 0x0b07 C low byte register bit function r/w description reset 7 ? 0 mea_win_v_ st [7:0] r/w input measurement window definition: vertical length - low dah 0x0b08 C measurement input selection, measurement start register bit function r/w description reset 7 ? 6 meas_sel r/w measurement input selection 0,1 = main path 2: pip 3: pip2 0 5 ? 4 reserved r/w reserved 0 3 ? 2 field_sel r/w field select for input measurement 0 = odd field only 1 = even f ield only 2,3 = disregard field 0 1 rdlock r/w lock the data while reading out - 0 startm r/w startm start input measurement. this bit is self-cleared a fter the measurement is done. 0 0x0b09 C measurement option, input change detectio n register bit function r/w description reset 7 reserved r/w reserved - 6 ? 4 noise_mask r/w noise mask bits for each of th e 3 lsb input signals. 0 3 ? 1 err_toler r/w error tolerance before assertin g ?change detected? status 000: exact match 001: up to 4 counts 0 10: u p to 8 counts 011: up to 16 counts 100: up to 32 counts 101: up to 64 counts 110: up to 1 28 counts 111: up to 256 counts. 0 0 endet r/w endet enable input vsync, hsync period change/loss detect ion. when this bit is set, the internal circuitry will p erform new measurements. the new results are compared against the results retained in the re gisters obtained by the most recent ?startm? measurement. 0 0x0b0a C measurement option register bit function r/w description reset 7 ? 4 threshold_ for_act_de t r/w threshold value for input active region detecti on. each increment increases the threshold value by 16. 3 3 enalu r/w enable luminance measurement. 0 2 ? 1 nofsel r/w noise filter selection for luminan ce measurement. 0 0 de_mea r/w de measurement enable. 0 TW8823 ? tft flat panel controller techwell, inc. 221 rev a 11/20/2009 0x0b10 ~ 0x0b13 phase_r registers 0x0b10 C byte 3 register bit function r/w description reset 7 ? 0 phase_r_b3 r/w phase measurement result - red 0 0x0b11 C byte 2 register bit function r/w description reset 7 ? 0 phase_r_b2 r/w phase measurement result - red 0 0x0b10 C byte 1 register bit function r/w description reset 7 ? 0 phase_r_b1 r/w phase measurement result - red 0 0x0b13 C byte 0 register bit function r/w description reset 7 ? 0 phase_r_b0 r/w phase measurement result - red 0 0x0b14 ~ 0x0b17 phase_g registers 0x0b14 C byte 3 register bit function r/w description reset 7 ? 0 phase_g_b3 r/w phase measurement result - gre en 0 0x0b15 C byte 2 register bit function r/w description reset 7 ? 0 phase_g_b2 r/w phase measurement result - gre en 0 0x0b16 C byte 1 register bit function r/w description reset 7 ? 0 phase_g_b1 r/w phase measurement result - gre en 0 0x0b17 C byte 0 register bit function r/w description reset 7 ? 0 phase_g_b0 r/w phase measurement result - gre en 0 TW8823 ? tft flat panel controller techwell, inc. 222 rev a 11/20/2009 0x0b18 ~ 0x0b1b phase_b registers 0x0b18 C byte 3 register bit function r/w description reset 7 ? 0 phase_b_b3 r/w phase measurement result - blu e 0 0x0b19 C byte 2 register bit function r/w description reset 7 ? 0 phase_b_b2 r/w phase measurement result - blu e 0 0x0b1a C byte 1 register bit function r/w description reset 7 ? 0 phase_b_b1 r/w phase measurement result - blu e 0 0x0b1b C byte 0 register bit function r/w description reset 7 ? 0 phase_b_b0 r/w phase measurement result - blu e 0 0x0b1c C minimum_r register bit function r/w description reset 7 ? 0 min_r r/w minimum measured red value 0 0x0b1d C minimum_g register bit function r/w description reset 7 ? 0 min_g r/w minimum measured green value 0 0x0b1e C minimum_b register bit function r/w description reset 7 ? 0 min_b r/w minimum measured blue value 0 0x0b1f C maximum_r register bit function r/w description reset 7 ? 0 max_r r/w maximum measured red value 0 0x0b20 C maximum_g register bit function r/w description reset 7 ? 0 max_g r/w maximum measured green value 0 0x0b21 C maximum_b register bit function r/w description reset 7 ? 0 max_b r/w maximum measured blue value 0 TW8823 ? tft flat panel controller techwell, inc. 223 rev a 11/20/2009 0x0b22 ~ 0x0b23 vertical period registers 0x0b22 C high byte register bit function r/w description reset 7 ? 0 v_period [15:8] r/w vertical period measured 0 0x0b23 C low byte register bit function r/w description reset 7 ? 0 v_period [7:0] r/w vertical period measured (in unit of input hsync) 0 0x0b24 ~ 0x0b25 horizontal period registers 0x0b24 C high byte register bit function r/w description reset 7 ? 0 h_period [15:8] r/w horizontal period measured 0 0x0b25 C low byte register bit function r/w description reset 7 ? 0 h_period [7:0] r/w horizontal period measured (in unit of 27 mhz clock) 0 0x0b26 ~ 0x0b27 hsync rise to fall registers 0x0b26 C high byte register bit function r/w description reset 7 ? 0 h_rise_to_f all [15:8] r/w input hsync rising edge to falling edge 0 0x0b27 C low byte register bit function r/w description reset 7 ? 0 h_rise_to_f all [7:0] r/w input hsync rising edge to falling edge (in unit of input clock) 0 0x0b28 ~ 0x0b29 hsync rise to horizontal active en d 0x0b28 C high byte register bit function r/w description reset 7 ? 0 h_rise_to_a ct_end [15:8] r/w input hsync rising edge to input horizontal act ive end 0 0x0b29 C low byte register bit function r/w description reset 7 ? 0 h_rise_to_a ct_end [7:0] r/w input hsync rising edge to input horizontal act ive end (in unit of input clock) 0 TW8823 ? tft flat panel controller techwell, inc. 224 rev a 11/20/2009 0x0b2a ~ 0x0b2b vsync high width registers 0x0b2a C high byte register bit function r/w description reset 7 ? 0 v_pulsew [15:8] r/w input vsync (logic) high width 0 0x0b2b C low byte register bit function r/w description reset 7 ? 0 v_pulsew [7:0] r/w input vsync (logic) high width (in unit of input hsync) 0 0x0b2c ~ 0x0b2d vsync rise position registers 0x0b2c C high byte register bit function r/w description reset 7 ? 0 v_rise_pcnt [15:8] r/w input vsync rising edge position in one input h sync period 0 0x0b2d C low byte register bit function r/w description reset 7 ? 0 v_rise_pcnt [7:0] r/w input vsync rising edge position in one input h sync period (in unit of input clock) 0 0x0b2e ~ 0x0b2f horizontal active starting pixel p osition i registers 0x0b2e C high byte register bit function r/w description reset 7 ? 0 h_act_st_mi n[15:8] r/w horizontal active region starting position 0 0x0b2f C low byte register bit function r/w description reset 7 ? 0 h_act_st_mi n[7:0] r/w horizontal active region starting position (in unit of input clock) 0 0x0b30 ~ 0x0b31 horizontal active starting pixel p osition ii registers 0x0b30 C high byte register bit function r/w description reset 7 ? 0 h_act_st_m ax [15:8] r/w horizontal active region starting position 0 0x0b31 C low byte register bit function r/w description reset 7 ? 0 h_act_st_m ax [7:0] r/w horizontal active region starting position (in unit of input clock) 0 TW8823 ? tft flat panel controller techwell, inc. 225 rev a 11/20/2009 0x0b32 ~ 0x0b33 horizontal active ending pixel pos ition i registers 0x0b32 C high byte register bit function r/w description reset 7 ? 0 h_act_end_ min [15:8] r/w horizontal active region ending position 0 0x0b33 C low byte register bit function r/w description reset 7 ? 0 h_act_end_ min [7:0] r/w horizontal active region ending position (in unit of input clock) 0 0x0b34 ~ 0x0b35 horizontal active ending pixel pos ition ii register 0x0b34 C high byte register bit function r/w description reset 7 ? 0 h_act_end_ max [15:8] r/w horizontal active region ending position 0 0x0b35 C low byte register bit function r/w description reset 7 ? 0 h_act_end_ max [7:0] r/w horizontal active region ending position (in unit of input clock) 0 0x0b36 ~ 0x0b37 vertical active starting line i re gisters 0x0b36 C high byte register bit function r/w description reset 7 ? 0 v_act_st_1 [15:8] r/w vertical active starting line number 0 0x0b37 C low byte register bit function r/w description reset 7 ? 0 v_act_st_! [7:0] r/w vertical active starting line number (in unit of input hsync) 0 0x0b38 ~ 0x0b39 vertical active starting line ii r egisters 0x0b38 C high byte register bit function r/w description reset 7 ? 0 v_act_st_2 [15:8] r/w vertical active starting line number 0 0x0b39 C low byte register bit function r/w description reset 7 ? 0 v_act_st_2 [7:0] r/w vertical active starting line number (in unit of input hsync) 0 TW8823 ? tft flat panel controller techwell, inc. 226 rev a 11/20/2009 0x0b3a ~ 0x0b3b vertical active ending line i regi sters 0x0b3a C high byte register bit function r/w description reset 7 ? 0 v_act_end_ 1 [15:8] r/w vertical active ending line number 0 0x0b3b C low byte register bit function r/w description reset 7 ? 0 v_act_end_! [7:0] r/w vertical active ending line number (in unit of input hsync) 0 0x0b3c ~ 0x0b3d vertical active ending line ii reg isters 0x0b3c C high byte register bit function r/w description reset 7 ? 0 v_act_end_ 2 [15:8] r/w vertical active ending line number 0 0x0b3d C low byte register bit function r/w description reset 7 ? 0 v_act_end_ 2 [7:0] r/w vertical active ending line number (in unit of input hsync) 0 0x0b3e ~ 0x0b3f fifo read starting position regist ers 0x0b3e C high byte register bit function r/w description reset 7 ? 0 h_pcnt_fifo _rd_st [15:8] r/w fifo read starting position 0 0x0b3f low byte register bit function r/w description reset 7 ? 0 h_pcnt_fifo _rd_st [7:0] r/w fifo read starting position 0 0x0b40 C liminance value C minimum register bit function r/w description reset 7 ? 0 lum_min r/w minimum measured luminance value 0 0x0b41 C lim inance value C maximum register bit function r/w description reset 7 ? 0 lum_max r/w maximum measured luminance value 0 0x0b42 C liminance value C average register bit function r/w description reset 7 ? 0 lum_ave r/w average measured luminance value 0 TW8823 ? tft flat panel controller techwell, inc. 227 rev a 11/20/2009 0x0b43 ~ 0x0b45 vertical period in 27 mhz register s 0x0b43 C high byte register bit function r/w description reset 7 ? 0 v_period_27 mh [23:16] r/w vertical period measured using 27 mhz clock 0 0x0b44 C mid byte register bit function r/w description reset 7 ? 0 v_period_27 mh [15:8] r/w vertical period measured using 27 mhz clock 0 0x0b45 C low byte register bit function r/w description reset 7 ? 0 v_period_27 mh [7:0] r/w vertical period measured using 27 mhz clock 0 TW8823 ? tft flat panel controller techwell, inc. 228 rev a 11/20/2009 lcdc C ddr memory control 0x0c00 C ddr memory control register bit function r/w description reset 7-6 reserved - 5 ddr_dqs_se l0[5] r/w 1: select delay line for dqs delay, 0: select d ll for dqs delay 0 4-0 ddr_dqs_se l0[4:0] r/w when [5] = 1, [1:0] specify delay by delay line, 0 : 0.5ns, 1 : 0.75ns, 2 : 1.00ns, 3 : 1.25ns when [5] = 0, [4:0] specify delay by dll. 1 unit is 1/32 phase delay. 00 0x0c01 C ddr memory control register bit function r/w description reset 7-6 reserved - 5 ddr_dqs_se l1[5] r/w 1: select delay line for dqs delay, 0: select d ll for dqs delay 0 5-0 ddr_dqs_se l1[4:0] r/w when [5] = 1, [1:0] specify delay by delay line, 0 : 0.5ns, 1 : 0.75ns, 2 : 1.00ns, 3 : 1.25ns when [5] = 0, [4:0] specify delay by dll. 1 unit is 1/32 phase delay. 00 0x0c02 C ddr mem ory control register bit function r/w description reset 7-5 ddr_clko_s el r/w memory clock output selection (only for fpga) 1 4-0 ddr_clk90_ sel r/w select the phase of 90 degree clk generated by dll. the phase is ddr_clk90_sel/32 08 0x0c03 C ddr memory control register bit function r/w description reset 7-4 dll_tst_sel r/w select the dll test output signal 0 3 reserved - 2 dll_tst r/w 1: bypass all dll or delay line 0 1-0 dll_tap_s r/w select the dll taps 0 0x0c04 C ddr memory control register bit function r/w description reset 7 dll_rstn r/w software reset only for dll (self return to 0) 0 6-0 reserved r/w - 0x0c05 C ddr memory control register bit function r/w description reset 7 rd_ph r/w select dqs or ~dqs as read clock to latch dq 0 6-4 reserved - 3-2 ddr_dqs_dl y r/w select dqs valid read data cycle delay number 2 1-0 ddr_wrnop r/w ddr read to write address additional nop cycles 0 TW8823 ? tft flat panel controller techwell, inc. 229 rev a 11/20/2009 0x0c06 C ddr memory control register bit function r/w description reset 7-4 ddr_t_rc r/w t_rc timing a 3-0 ddr_t_ras r/w t_ras timing 7 0x0c07 C ddr memory control register bit function r/w description reset 7-4 ddr_t_rfc r/w t_rfc timing b 3 reserved - 2-0 ddr_t_rp r/w t_rp timing 4 0x0c08 C ddr memory control register bit function r/w description reset 7 reserved - 6-4 ddr_t_rcd r/w t_rcd timing 4 3 reserved - 2-0 ddr_t_wr r/w t_wr timing 3 0x0c09 C ddr memory control register bit function r/w description reset 7 reserved - 6-4 ddr_refres h r/w ddr refresh timing control 0 3 init_byp ddr initialization bypass (1: for simulation) 0 2-0 ddr_b_leng th r/w ddr burst length 3 0x0c0a C ddr memory control register bit function r/w description reset 7 ddr_tst r/w 1: bypass all dll or delay line 0 6-4 ddr_cas_la t r/w ddr cas latency 7 3 samsng r/w internal test mode 0 2-0 reserved r/w - TW8823 ? tft flat panel controller techwell, inc. 230 rev a 11/20/2009 0x0c0b C ddr memory control register bit function r/w description reset 7 ddr_wtr r/w 1: ddr write to read turn around cycle needed, 0: no turn around cycle 0 6 ddr_btyp r/w external ddr burst type (for initialization pur pose) 0 5 ddr_dvst r/w configure external ddr driving strength (for in itialization purpose) 0 4 dll_en r/w enable dll in the external ddr memory (for ini tialization purpose) 1 3 reserved - 2-0 ddr_size r/w ddr size 1 0x0c0c C ddr memory control register bit function r/w description reset 7 ddr_rstn r/w software reset only for ddr logic (auto return to 0) 0 6-0 reserved r/w - TW8823 ? tft flat panel controller techwell, inc. 231 rev a 11/20/2009 lcdc C aux control 0x0cf0 C ddr direct r/w control register bit function r/w description reset 7-0 aux_rwdat r/w read/write data to/from ddr 00 0x0cf1 C ddr direct r/w control register bit function r/w description reset 7 fifo_rst r/w 1: read/write fifo reset, self clear 0 6-2 reserved r/w - 1 fifo_empty r 1: fifo status is empty 1 0 fifo_full r 1: fifo status is full 0 0x0cf2 C ddr direct r/w control register bit function r/w description reset 7-0 aux_addr[23 :16] r/w address for burst read/write to/from ddr 00 0x0cf3 C ddr direct r/w control register bit function r/w description reset 7-0 aux_addr[15 :8] r/w address for burst read/write to/from ddr 00 0x0cf4 C ddr direct r/w control register bit function r/w description reset 7-0 aux_addr[7: 0] r/w address for burst read/write to/from ddr 00 0x0cf5 C ddr direct r/w control register bit function r/w description reset 7-3 reserved - 7-0 aux_length [10:8] r/w length of the burst read/write to/from ddr. the maximum length is 1024. 00 0x0cf6 C ddr direct r/w control register bit function r/w description reset 7-0 aux_length [7:0] r/w length of the burst read/write to/from ddr. the maximum length is 1024. 00 TW8823 ? tft flat panel controller techwell, inc. 232 rev a 11/20/2009 0x0cf7 C ddr direct r/w control register bit function r/w description reset 7-2 reserved r/w - 1 aux_rd r/w ddr read command (self cleared) 0 0 aux_wr r/w ddr write command (self cleared) 0 TW8823 ? tft flat panel controller techwell, inc. 233 rev a 11/20/2009 ccfl and ledc control 0x0d0 C ccfl/led control i bit function r/w description reset 7-1 reserved - reserved - 0 biasctl r/w 0 0x0d01 C ccfl/led control i bit function r/w description reset 7 oven r/w ccfl over voltage feedback control 0 = disable 1 = enable 1 6 oien r/w ccfl over current feedback control 0 = disable 1 = enable 1 5 uien r/w ccfl under current feedback control 0 = disable 1 = enable 1 4 fben r/w ccfl feedback loop control 0 = open loop 1 = close loop 1 3 lockv r/w ccfl dimming frequency 0 = set by fdim 1 = lock ed to panel vertical sync 0 2 lockh r/w ccfl pwm frequency 0 = set by fpwm 1 = locked to panel horizontal frequency 0 1 ccflenb r/w ccfl analog sense 0 = power down 1 = power up. 1 0 ccflden r/w ccfl out 0 = disable. 1 = enable. 0 0x0d02 C ccfl threshold and ledc control bit function r/w description reset 7-6 lvt r/w ccfl lamp voltage threshold 2 5-4 lilt r/w ccfl lamp low current threshold 2 3-0 lit / vfb_vop r/w ccfl lamp normal current threshold or ledc vfb / vop selection when ccfl_ledc_den set to 0, this is lamp normal cu rrent threshold. when ccfl_ledc_den set to 1, bits[3:2] is feedback reference voltage selection (vfb) and bits[1:0] is voltage overdrive protection selec tion(vop). vfb : 00 = 0.7v, 01= 0.55v, 10= 0.4v, 11= 0.25v vop : 00= 0.7v, 01 = 0.55v, 10= 0.4v, 11= 0.25v d TW8823 ? tft flat panel controller techwell, inc. 234 rev a 11/20/2009 0x0d03 C ccfl/led control ii bit function r/w description reset 7 led_dig_en r/w ledc digital 0 = disable 1 = enable 0 6 ledc_ apdwn r/w ledc analog block power down 0 = normal 1 = power down 0 5-4 cc_led_st r/w ccfl or ledc status 0 3-0 lstp r/w ccfl or ledc feedback gain control wit h 1 being the smallest gain. 4 0x0d04 C ccfl/ledc pwm bit function r/w description reset 7-0 fpwm r/w ccfl pwm control frequency fpwm[7:0] : ccfl pwm (6..75mhz / fpwm) fpwm[6:0] : led pwm (13.5mhz / fpwm) 70 0x0d05 C ccfl/led dim frequency bit function r/w description reset 7-0 fdim r/w ccfl or ledc dimming frequency control . freq = 13.18khz / fdim 84 0x0d06 C ccfl/led dim control bit function r/w description reset 7 reserved - reserved - 6-0 ddim r/w ccfl or ledc dimming control. 0 = full brightness, 7f = lowest brightness 00 0x0d07 C ccfl/led pwmtop bit function r/w description reset 7-0 pwmtop r/w ccfl or ledc pwm top / min out 04 TW8823 ? tft flat panel controller techwell, inc. 235 rev a 11/20/2009 0x0d10 C control signal generation method register (logic level: 1.8v) bit function r/w description relative pin reset 7 pd r/w adc power down. start with power down mode 1 6 rst r/w adc reset. pusle needs to be longer than 1clk cycle 0 5 start r/w adc start. pusle needs to be longer than 1clk cycle 0 4 pen_irq r/w pen interrupt detect 0 3 rdy_irq r/w ready interrupt detect 0 2:0 a<2:0> r/w mode selection 000 x position measurement 001 z1 010 z2 011 y position measurement 100 auxiliary 0 101 auxiliary 1 110 auxiliary 2 111 auxiliary 3 000 TW8823 ? tft flat panel controller techwell, inc. 236 rev a 11/20/2009 touch screen control 0x0d11 C control signal generation method register (logic level: 1.8v) 0x0d12 C tsc adc data output bit function r/w description relative pin reset 7:0 tcs_adout r/w tsc_out[11:4] 0 0x0d13 C tsc adc data output bit function r/w description relative pin reset 7:4 - - - - - 3:0 tcs_adout r/w tsc_out[3:0] 0 bit function r/w description relative pin reset 7 rdyint_enb r/w ready interrupt enable. to activate the interrupt, program pd=0 and rdyint_enb=1 0 6 penint_enb r/w pen interrupt enable. to activate the interrupt, pr ogram pd=0 and penint_enb=1 0 5:3 r_sel<2:0> r/w r selection for touch detection sensitivity 000: 150k, 001: 130k, 010: 110k, 011: 90k 100: 70k, 101: 50k, 110: 30k, 111: 10k 000 2-0 test_adc r/w adc test mode control 000: disable 001: disable 010: disable 011: disable 100: buffered internal comparator input 101: vmid 110: comp out 111: regen clock 000 TW8823 ? tft flat panel controller techwell, inc. 237 rev a 11/20/2009 0x0d14 C tsc start and clock bit function r/w description relative pin reset 3 conti_smp r/w 0: start by register command 1: continuous sample for tsc adc regardless of register start signal 0 2:0 tcs_cksel r/w divided factor for tsc adc clock 0 : divide by 2 1 : divide by 4 2 : divide by 8 3 : divide by 16 4 : divide by 32 5 : divide by 64 6 : divide by 128 7 : divide by 256 0 TW8823 ? tft flat panel controller techwell, inc. 238 rev a 11/20/2009 0x00 Cadc output read only register (logic level: 1 .8v) bit function r/w description relative pin reset 16:4 adc output r adc output bit<16>: msb, bit<4> lsb 0 3:0 filler r not used, assigned to zero 0 note: this read only register is implemented on the top level of this analog ip. the raw data will be read and placed in this register. TW8823 ? tft flat panel controller techwell, inc. 239 rev a 11/20/2009 lvds configuration registers 0xd40 C mode 1 setting register bit function r/w description reset 7-5 ctl_mapsel r/w control signal order in serial d ata sequence out 3'b000 : {de, vsync, hsync}; 3'b001 : {vsync, hsync, de}; 3'b010 : {hsync, de, vsync}; 3'b100 : {de, hsync, vsync}; 3'b101 : {hsync, vsync, de}; 3'b110 : {vsync, de, hsync}; default : {de, vsync, hsync}; 0 4-3 bit_perpix r/w bit per pixel of data bus 00: 3bit, 01 : 4bit, 10 : 5bit, 11: reserved 0 2 lvds_op r/w lvds operation 0 : lvds no operation (tcon selected) 1 : lvds operation 0 1 fab_tst r/w lvds test mode 0 : normal operation mode 1 : lvds test mode 0 0 lcd_tst r/w lcd panel test mode 0 : normal operation mode 1 : lcd panel test mode 0 0xd41 C mode 2 setting register bit function r/w description reset 7 rd_sh r/w road/shift signal polarity selection 0 : active low 1 : active high 0 6 swap_ch r/w channel swap in dual channel lvds 0 5 mx_rev_dcb r/w reverse dc balance for maxim mode 0 4 rev_bit r/w reversed data output 0 : normal data output format 1 : reversed data output format 0 3 dcb_pol r/w dc balance polarity 0 2 dc_bal r/w dc balance enable 0 1 dual_ch r/w dual channel enable 0 0 maxim_sel r/w output mapping 1 : output data mapping same as maxim or thine lvds interface protocols. 0 : output data mapping same as national semico nductor interface protocols. 0 0xd42 C mode 3 setting register bit function r/w description reset 7-6 cp_sel r/w charge pump control 00 5-4 lp_sel r/w low pass filter control 00 3 - r/w reserved 0 2 - r/w reserved 0 1-0 sel_lvds r/w lvds type selection 00 TW8823 ? tft flat panel controller techwell, inc. 240 rev a 11/20/2009 remocon_rx 0xda0 C remocon control0 bit function r/w description reset 6 rempol r/w polarity inverse of irrx pin input sig nal 1 : inverse 0 : non-inverse 0x1 5-1 htref r/w ht6230 type remocon signal clock gene ration reference. typical value is 0x13 and some ht6230 type remocon is 0x12. 0x13 0 htini[8] r/w ht6230 data sample start timing. 0x0 0xda1 C remocon control1 bit function r/w description reset 7-0 htini[7:0] r/w ht6230 data sample start timing. 0xb0 0xda2 C remocon enable bit function r/w description reset 0 remen r/w remocon receiver enable signal 1 : enable, 0 : diabale 0x0 0xda3 C remocon interrupt bit function r/w description reset 3 remerror_ flag r/w 1 : there are some errors during receiving remo con data or non-supported remocon data received. 0 : the other case. * cleared by writing ?1? 0 2 updlint_flag r/w 1 : upd type remocon?s ?kept dep ressed? signal(keep pushing same button signal) is received without command data. 0 : the other case * cleared by writing ?1? 0 1 updint_flag r/w 1 : upd type remocon data is rece ived. 0 : the other case. * cleared by writing ?1? 0 0 htint_flag r/w 1 : ht type remocon data is receiv ed. 0 : the other case. * cleared by writing ?1? 0 TW8823 ? tft flat panel controller techwell, inc. 241 rev a 11/20/2009 0xda4 C htsystem bit function r/w description reset 5 htcontrol r 1 control bits from ht6230 type remoc on signal input 4-0 htsystem r 5 system bits from ht6230 type remoc on signal input 0xda5 C htcommand bit function r/w description reset 5-0 htcommand r 6 command bits from ht6230 type rem ocon signal input 0xda6 C updreg3 bit function r/w description reset 7-0 updreg[31:2 4] r 4th received byte from upd type remocon signal in put. it is inversion data code. 0xda7 C updreg2 bit function r/w description reset 7-0 updreg[23:1 6] r 3rd received byte from upd type remocon signal in put. it is data code. 0xda8 C updreg1 bit function r/w description reset 7-0 updreg[15:8] r 2nd received byte from upd type remocon signal input. it is custom code2. 0xda9 C updreg0 bit function r/w description reset 7-0 updreg[7:0] r 1 st received byte from upd type remocon signal input. it is custom code. 0xdaa C rempi bit function r/w description reset 0 rempi r irrx pin input signal for remocon receive r software. 0xdab C remclkref bit function r/w description reset 7-0 remclkref[ 15:8] r/w upper byte remclkref 0x00 0xdac C remclkref bit function r/w description reset 7-0 remclkref[ 7:0] r/w lower byte remclkref 0x27 TW8823 ? tft flat panel controller techwell, inc. 242 rev a 11/20/2009 0xdad C updhten bit function r/w description reset 3 upden r/w nec type ir receiver enable 0x1 2 hten r/w ht type ir receiver enable 0x1 1-0 usample[9:8] r/w msb 2bits of upd remocon data sample timing value. 0x0 0xdae C usample bit function r/w description reset 7-0 usample[7:0] r/w lsb 8bits of upd remocon data sample timing value. 0x1b 0xdaf C ulleader bit function r/w description reset 1-0 ulleader[9: 8] r/w msb 2 bits of upd remocon leader code low perio d control value 0x0 0xdb0 C ulleader bit function r/w description reset 7-0 ulleader[7: 0] r/w lsb 8 bits of upd remocon leader code low peri od control value 0x36 0xdb1 C uhleader bit function r/w description reset 1-0 uhleader[9:8] r/w msb 2 bits of upd remocon lea der code high period control value 0x0 0xdb2 C uhleader bit function r/w description reset 7-0 uhleader[7:0] r/w lsb 8 bits of upd remocon le ader code high period control value 0x36 TW8823 ? tft flat panel controller techwell, inc. 243 rev a 11/20/2009 lcdc C lopor 0xdc0 C lso power down register bit function r/w description reset 7-1 reserved - reserved 0 0 pd_lso r/w power down for lso 0 0xdc1 C por power down register bit function r/w description reset 7-2 reserved - reserved 0 1 dis_dly r/w disable delay count for por 0 0 pd_por r/w power down for por 0 TW8823 ? tft flat panel controller techwell, inc. 244 rev a 11/20/2009 lcdc C pll (panel clock) 0x0dd0 C pll control register bit function r/w description reset 7 - 5 ip_p r/w charge pump current control for pclk 4 4 edge_sel_p r/w edge select for pclk sspll 0 3 - 0 freq_p[19:16 ] r/w pclk oscillation frequency calculation freq_p[1 9:16]. total 20bits. pclk pll oscillation frequency = 108mhz * freq_p / 2 ^ 17 / 2^ post_p 0 0x0dd1 C pll control register bit function r/w description reset 7 - 0 freq_p[15:8] r/w freq_p[15:8] 00 0x0dd2 C pll control register bit function r/w description reset 7 - 0 freq_p[7:0] r/w freq_p[7:0] 00 0x0dd3 C pll control register bit function r/w description reset 7 - 0 ssfreq_p[7: 0] r/w pclk spread spectrum modulation frequency ssfreq_p[7:0] spread spectrum modulation frequency = 27mhz * ssfr eq_p / 2^16 00 0x0dd4 C pll control register bit function r/w description reset 7 - 4 ssg_p[3:0] r/w pclk variance of spread spectr um. ssg_p[3:0] frequency deviation control for pclk : the max percentage of frequency deviation is given by following equation. dev = 2^8 * ssg_p / 2^ssd / 2^freq_p * 100 % 0 3 - 2 vco_p r/w pclk vco[1:0] 0 = 13.5 ~ 27mhz, 1 = 27 ~ 54 mhz 2 = 54 ~ 108mhz, 3 = 108 ~ 133mhz 0 1 - 0 post_p r/w pclk post[1:0] 0 TW8823 ? tft flat panel controller techwell, inc. 245 rev a 11/20/2009 0x0dd5C pll control register bit function r/w description reset 7 pd_p r/w freq. synthesizer power down for pclk 0 = normal operation 1 = off 0 6 reserved - reserved - 5 - 4 cpx4_p r/w cp_x4 for pclk sspll 0 3 - 2 lpx4_p r/w lp_x4 for pclk sspll 0 1 - 0 lpx8_p r/w lp_x8 for pclk sspll 0 0x0dd6C pll control register bit function r/w description reset 7 - 6 reserved - reserved - 5 - 3 reserved - reserved 0 2 - 0 dgain_p r/w dgain for panel clock pll 0 TW8823 ? tft flat panel controller techwell, inc. 246 rev a 11/20/2009 lcdc C pll (memory clock) 0x0dd8 C pll control register bit function r/w description reset 7 - 5 ip_m[2:0] r/w charge pump current control for mclk 0 4 edge_sel_ m r/w edge select for mclk sspll 0 3 - 0 freq_m[19:1 6] r/w mclk oscillation frequency calculation freq_m[19:16 ]. total 20 bits. mclk pll oscillation frequency = 108mhz * freq_m / 2 ^ 17 / 2^ post_m 0 0x0dd9 C pll control register bit function r/w description reset 7 - 0 freq_m[15:8] r/w freq_m[15:8] 00 0x0ddaC pll control register bit function r/w description reset 7 - 0 freq_m[7:0] r/w freq_m[7:0] 00 0x0ddbC pll control register bit function r/w description reset 7 - 0 ssfreq_m[7: 0] r/w mclk spread spectrum modulation frequency. ssfreq_m[7:0] spread spectrum modulation frequency = 27mhz * ssf req_m / 2^16 00 0x0ddcC pll control register bit function r/w description reset 7 - 4 ssg_m[3:0] r/w mclk variance of spread spectr um. ssg_m[3:0] frequency deviation control for mclk : the max percentage of frequency deviation is given by following equation. dev = 2^8 * ssg_m / 2^ssd / 2^freq_m * 100 % 0 3 - 2 vco_m r/w mclk vco[1:0] 0 = 13.5 ~ 27mhz, 1 = 27 ~ 54 mhz 2 = 54 ~ 108mhz, 3 = 108 ~ 133mhz 0 1 - 0 post_m r/w mclk post[1:0] 0 TW8823 ? tft flat panel controller techwell, inc. 247 rev a 11/20/2009 0x0dddC pll control register bit function r/w description reset 7 pd_m r/w freq. synthesizer power down for mclk 0 = normal operation 1 = off 0 6 reserved - reserved 5 - 4 cpx4_m r/w cp_x4 for mclk sspll 0 3 - 2 lpx4_m r/w lp_x4 for mclk sspll 0 1 - 0 lpx8_m r/w lp_x8 for mclk sspll 0 0x0ddeC pll control register bit function r/w description reset 7 - 6 reserved - reserved - 5 - 3 reserved - reserved 0 2 - 0 dgain_m r/w dgain for memory clock pll 0 lcdc C dac 0x0de0C dac control register bit function r/w description reset 7-4 dacgain r dac gain control. 0 3-1 dac_vcm r/w dac output common mode voltage sele ction. 000 = 1.0 v 001 = 1.25 v 010 =1.375 v 011 = 1.625 v 100 = 2.0 v 101 = 2.50 v 110 = not supported 111 = not supported 0 0 dacpd r/w dac power down 0 TW8823 ? tft flat panel controller techwell, inc. 248 rev a 11/20/2009 mcu 0x0f00 C spi flash mode control register bit function r/w description reset 7-3 reserved - reserved - 2-0 spi_mode r/w spi flash read mode 000:slow, 001:fast, 010:dual, 011:quad, 100:dual-io, 101:quad-io 000 0x0f01 C mcu clock control register bit function r/w description reset 7-6 reserved - reserved - 5-4 mcu_ck_sel r/w mcu clock selection 0=system clock (27mhz) 1=internal r-c oscillator (32khz) 2=pclk 3=reserved 00 3 reserved r/w reserved - 2-0 mcu_ck_div r/w pll clock divider 0=1.0 (108mhz) 1=1.5 (72mhz) 2=2.0 (54mhz) 3=2.5 (43.2mhz ) 4=3.0 (36mhz) 5=3.5 (30.8mhz ) 6=4.0 (27mhz) 7=5.0 (13.5mhz ) 110 0x0f02 C spi clock control register bit function r/w description reset 7-6 reserved r/w reserved - 5-4 spi_ck_sel r/w spi clock selection 0=system clock (27mhz) 1=internal r-c oscillator (32khz) 2=pclk 3=reserved 00 3 reserved r/w reserved - 2-0 spi_ck_div r/w pll clock divider 0=1.0 (108mhz) 1=1.5 (72mhz) 2=2.0 (54mhz) 3=2.5 (43.2mhz ) 4=3.0 (36mhz) 5=3.5 (30.8mhz ) 6=4.0 (27mhz) 7=5.0 (13.5mhz ) 110 TW8823 ? tft flat panel controller techwell, inc. 249 rev a 11/20/2009 0x0f03 C dma control register bit function r/w description reset 7 index_sel r/w read/write data buffer source/desti nation 0=default (reg0xf10) 1=assigned by buffer in dex 0 6 xmem_dma r/w read/write destination 0=mcu xdata 1=chip register 1 5-4 dma_reg_mod e r/w read/write access mode 00=increase 01=decrease 10=fix 11=reserved 00 3 dma_nonv r/w start mode 0=immediately 1=at vertical blank 0 2-0 wr_cnt_num r/w command write byte count 0 0x0f04 C flash busy control register bit function r/w description reset 7-4 reserved - reserved - 3 reserved - reserved 0 2 busy_check r/w busy check 0=no busy check 1=busy check after command. wait until busy is clea red 0 1 wr_mode r/w spi dma/cmd mode 0=read, 1=write 0 0 dma_str r/w start command execution. self cleared . write ?1? = start write ?0? = stop read ?1? = busy read ?0? = ready 0 0x0f05 C wait control register bit function r/w description reset 7-4 dma_wait r/w dma read wait cycle 1000 3-0 spi_wait r/w spi read/write wait cycle 0000 0x0f06 C dma page register bit function r/w description reset 7-0 dma_reg_pag e r/w buffer index page or memory start address high byte 06h 0x0f07 C dma index register bit function r/w description reset 7-0 index r/w buffer index or memory start address low byte 00h 0x0f08 C dma length mid byte register bit function r/w description reset 7-0 dma_length r/w read/write data count mid byte a fter command 00h TW8823 ? tft flat panel controller techwell, inc. 250 rev a 11/20/2009 0x0f09 C dma length low byte register bit function r/w description reset 7-0 dma_length r/w read/write data count low byte a fter command 00h 0x0f0a C dma command buffer1 register bit function r/w description reset 7-0 wr_reg1_rg r/w command buffer 1 00h 0x0f0b C dma command buffer2 register bit function r/w description reset 7-0 wr_reg2_rg r/w command buffer 2 00h 0x0f0c C dma command buffer3 register bit function r/w description reset 7-0 wr_reg3_rg r/w command buffer 3 00h 0x0f0d C dma command buffer4 register bit function r/w description reset 7-0 wr_reg4_rg r/w command buffer 4 00h 0x0f0e C dma command buffer5 register bit function r/w description reset 7-0 wr_reg5_rg r/w command buffer 5 00h 0x0f0f C clock switch wait control register bit function r/w description reset 7-0 clk_switch_ wait r/w clock switch wait count 1fh 0x0f10 C dma read/write buffer1 register bit function r/w description reset 7-0 buf1 r/w default read/write buffer 1 00h 0x0f11 C dma read/write buffer2 register bit function r/w description reset 7-0 buf2 r/w default read/write buffer 2 00h 0x0f12 C dma read/write buffer3 register bit function r/w description reset 7-0 buf3 r/w default read/write buffer 3 00h TW8823 ? tft flat panel controller techwell, inc. 251 rev a 11/20/2009 0x0f13 C dma read/write buffer4 register bit function r/w description reset 7-0 buf4 r/w default read/write buffer 4 00h 0x0f14 C dma read/write buffer5 register bit function r/w description reset 7-0 buf5 r/w default read/write buffer 5 00h 0x0f15 C dma read/write buffer6 register bit function r/w description reset 7-0 buf6 r/w default read/write buffer 6 00h 0x0f16 C dma read/write buffer7 register bit function r/w description reset 7-0 buf7 r/w default read/write buffer 7 00h 0x0f17 C dma read/write buffer8 register bit function r/w description reset 7-0 buf8 r/w default read/write buffer 8 00h 0x0f18 C spi flash status command register bit function r/w description reset 7-0 status_cmd_ rg r/w status command 05h 0x0f19 C spi flash busy control register bit function r/w description reset 7-4 reserved - reserved - 3 busy_pol r/w busy polarity 0=low 1=high 1 2-0 busy_bit r/w busy bit in status command 000 0x0f1a C dma length high byte register bit function r/w description reset 7-0 dma_length r/w read/write data count high byte after command 00h TW8823 ? tft flat panel controller techwell, inc. 252 rev a 11/20/2009 0x0f20 C mcu control register bit function r/w description reset 7 mcuen r mcu status 0=disabled 1=enabled - 6 srst_chip r/w mcu reset chip register 0 5 osd_dma r/w osd dma enable 0 4 reserved r/w reserved - 3 spi_en r/w spi enable 1 : enable, 0 : disable 1 2 cache_en r/w enable mcu code cache 0=disable, 1=enable 0 1 bootsel r/w mcu boot selection 0=spi, 1=internal rom 0 0 srst_mcu r/w reset mcu. isp has to be enabled bef ore set this. 0 0x0f21 C isp passcode register bit function r/w description reset 7-0 ispen r/w password for isp enabling write 0x55, 0xaa sequentially to enable isp 00h 0x0f22 C timer0 divider high byte register bit function r/w description reset 7-0 rg_dvidt0 r/w timer0 divider high byte 00h 0x0f23 C timer0 divider low byte register bit function r/w description reset 7-0 rg_dvidt0 r/w timer0 divider low byte 90h 0x0f24 C timer1 divider high byte register bit function r/w description reset 7-0 rg_dvidt1 r/w timer1 divider high byte 00h 0x0f25 C timer1 divider low byte register bit function r/w description reset 7-0 rg_dvidt1 r/w timer1 divider low byte 90h 0x0f26 C timer2 divider high byte register bit function r/w description reset 7-0 rg_dvidt2 r/w timer2 divider high byte 00h 0x0f27 C timer2 divider low byte register bit function r/w description reset 7-0 rg_dvidt2 r/w timer2 divider low byte 90h TW8823 ? tft flat panel controller techwell, inc. 253 rev a 11/20/2009 0x0f28 C timer3 divider high byte register bit function r/w description reset 7-0 rg_dvidt3 r/w timer3 divider high byte 00h 0x0f29 C timer3 divider low byte register bit function r/w description reset 7-0 rg_dvidt3 r/w timer3 divider low byte 0ch 0x0f2a C timer4 divider high byte register bit function r/w description reset 7-0 rg_dvidt4 r/w timer4 divider high byte 00h 0x0f2b C timer4 divider low byte register bit function r/w description reset 7-0 rg_dvidt4 r/w timer4 divider low byte 0ch 0x0f2c C osd dma busy check delay register bit function r/w description reset 7-0 osd_wait r/w osd dma busy check delay 02h mcu sfr register 0x9a C code bank address register bit function r/w description reset 7-0 rg_dvidt4 r/w program base address 0 0xfa C interrupt7~14 control register bit function r/w description reset 7-0 rg_dvidt4 r/w int14~int7 flag 0 0xfb C interrupt7~14 control register bit function r/w description reset 7-0 rg_dvidt4 r/w int14~int7 enable 0 0xfc C interrupt7~14 control register bit function r/w description reset 7-0 rg_dvidt4 r/w int14~int7 priority 0 TW8823 ? tft flat panel controller techwell, inc. 254 rev a 11/20/2009 0xfd C interrupt7~14 control register bit function r/w description reset 7-0 rg_dvidt4 r/w int14~int7 edge/level 0 0xfe C interrupt7~14 control register bit function r/w description reset 7-0 rg_dvidt4 r/w int14~int7 edge/level polarity 0 0xe2 C cache control register bit function r/w description reset 7-2 reserved - reserved - 1 rg_pwdn r/w power down cache 0 0 reserved - reserved - interrupt vector address *int7_sub_addr = 5'b01101; // 0x6b *int8_sub_addr = 5'b01110; // 0x73 *int9_sub_addr = 5'b01111; // 0x7b *int10_sub_addr = 5'b10000; // 0x83 *int11_sub_addr = 5'b10001; // 0x8b *int12_sub_addr = 5'b10010; // 0x93 *int13_sub_addr = 5'b10011; // 0x9b *int14_sub_addr = 5'b10100; // 0xa3 0x80 C sfr register bit function r/w description reset 7-0 p0 r/w port 0 ffh 0x81 C sfr register bit function r/w description reset 7-0 sp r/w stack pointer 07h 0x82 C sfr register bit function r/w description reset 7-0 dpl r/w data pointer 0 low 00h 0x83 C sfr register bit function r/w description reset 7-0 dph r/w data pointer 0 high 00h TW8823 ? tft flat panel controller techwell, inc. 255 rev a 11/20/2009 0x84 C sfr register bit function r/w description reset 7-0 dpl1 r/w data pointer 1 low 00h 0x85 C sfr register bit function r/w description reset 7-0 dph1 r/w data pointer 1 high 00h 0x86 C sfr register bit function r/w description reset 7-0 dps r/w data pointers select 00h 0x87 C sfr register bit function r/w description reset 7-0 pcon r/w power control 00h 0x88 C sfr register bit function r/w description reset 7-0 tcon r/w timer/counter control 00h 0x89 C sfr register bit function r/w description reset 7-0 tmod r/w timer mode control 00h 0x8a C sfr register bit function r/w description reset 7-0 tl0 r/w timer 0, low byte 00h 0x8b C sfr register bit function r/w description reset 7-0 tl1 r/w timer 1, low byte 00h 0x8c C sfr register bit function r/w description reset 7-0 th0 r/w timer 1, high byte 00h 0x8d C sfr register bit function r/w description reset 7-0 th1 r/w timer 1, high byte 00h TW8823 ? tft flat panel controller techwell, inc. 256 rev a 11/20/2009 0x8e C sfr register bit function r/w description reset 7-0 ckcon r/w clock control 07h 0x90 C sfr register bit function r/w description reset 7-0 p1 r/w port 1 ffh 0x91 C sfr register bit function r/w description reset 7-0 eif r/w extended interrupt flags 00h 0x92 C sfr register bit function r/w description reset 7-0 wtst r/w program memory wait-states 07h 0x93 C sfr register bit function r/w description reset 7-0 dpx0 r/w data page pointer 0 00h 0x95 C sfr register bit function r/w description reset 7-0 dpx1 r/w data page pointer 1 00h 0x98 C sfr register bit function r/w description reset 7-0 scon0 r/w uart0 control 00h 0x99 C sfr register bit function r/w description reset 7-0 sbuf0 r/w uart0 buffer 00h 0xa0 C sfr register bit function r/w description reset 7-0 p2 r/w port 2 00h 0xa8 C sfr register bit function r/w description reset 7-0 ie r/w interrupt enable 00h 0xb0 C sfr register bit function r/w description reset 7-0 p3 r/w port 3 ffh TW8823 ? tft flat panel controller techwell, inc. 257 rev a 11/20/2009 0xb8 C sfr register bit function r/w description reset 7-0 ip r/w interrupt priority 00h 0xc0 C sfr register bit function r/w description reset 7-0 scon1 r/w uart1 control 00h 0xc1 C sfr register bit function r/w description reset 7-0 sbuf1 r/w uart1 buffer 00h 0xc2 C sfr register bit function r/w description reset 7-0 ccl1 r/w timer2cc compare/capture 1 low byte 00h 0xc3 C sfr register bit function r/w description reset 7-0 cch1 r/w timer2cc compare/capture 1 high byte 00h 0xc4 C sfr register bit function r/w description reset 7-0 ccl2 r/w timer2cc compare/capture 2 low byte 00h 0xc5 C sfr register bit function r/w description reset 7-0 cch2 r/w timer2cc compare/capture 2 high byte 00h 0xc6 C sfr register bit function r/w description reset 7-0 ccl3 r/w timer2cc compare/capture 3 low byte 00h 0xc7 C sfr register bit function r/w description reset 7-0 cch3 r/w timer2cc compare/capture 3 high byte 00h 0xc8 C sfr register bit function r/w description reset 7-0 t2con r/w timer2cc control 00h TW8823 ? tft flat panel controller techwell, inc. 258 rev a 11/20/2009 0xc9 C sfr register bit function r/w description reset 7-0 t2if r/w timer2cc interrupt flag 00h 0xca C sfr register bit function r/w description reset 7-0 crcl r/w timer2cc capture/reload low byte 00h 0xcb C sfr register bit function r/w description reset 7-0 crch r/w timer2cc capture/reload high byte 00h 0xcc C sfr register bit function r/w description reset 7-0 tl2 r/w timer2cc low byte 00h 0xcd C sfr register bit function r/w description reset 7-0 th2 r/w timer2cc high byte 00h 0xce C sfr register bit function r/w description reset 7-0 ccen r/w timer2cc compare/ capture enable 00h 0xd0 C sfr register bit function r/w description reset 7-0 psw r/w program status word 00h 0xd8 C sfr register bit function r/w description reset 7-0 wdcon r/w watchdog control register 00h 0xe0 C sfr register bit function r/w description reset 7-0 acc r/w accumulator 00h 0xe8 C sfr register bit function r/w description reset 7-0 eie r/w extended interrupt enable 00h TW8823 ? tft flat panel controller techwell, inc. 259 rev a 11/20/2009 0xe9 C sfr register bit function r/w description reset 7-0 status r/w status register 00h 0xea C sfr register bit function r/w description reset 7-0 mxax r/w address register for movx @ri, a and m ovx a @ri 00h 0xeb C sfr register bit function r/w description reset 7-0 ta r/w timed access protection register 00h 0xf0 C sfr register bit function r/w description reset 7-0 b r/w b register 00h 0xf8 C sfr register bit function r/w description reset 7-0 eip r/w extended interrupt priority 00h 0xf9 C sfr register bit function r/w description reset 7-0 md0 r/w multiplication / division register 0 00h TW8823 ? tft flat panel controller techwell, inc. 260 rev a 11/20/2009 copyright notice this manual is copyrighted by techwell, inc. do not reproduce, transform to any other format, or send/ transmit any part of this documentation without the express written permission of techwell, inc. trademark acknowledgment silicon image, the silicon image logo, panellink ? is a registered trademarks of silicon image, inc. v esa ? is a registered trademark of the video electronics stand ards association. all other trademarks are the prop erty of their respective holders. disclaimer this document provides technical information for th e user. techwell, inc. reserves the right to modify the information in this document as necessary. the cust omer should make sure that they have the most recen t data sheet version. techwell, inc. holds no responsibili ty for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. techwell, inc. respects valid patent rights of third parties and does not infringe upon or assist others to infr inge upon such rights. life support policy techwell, inc. products are not authorized for use as critical components in life support devices or s ystems. revision history date revision note |
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